A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.

A resin having a small linear thermal expansion coefficient and a low absorbance is provided. The resin is characterized by including at least one structure selected from structures represented by the following general formulae (1) and (2):

##STR00001##

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

A display device and a manufacturing method thereof are provided. The display device includes: a first array substrate, a first opposite substrate, a second array substrate and a second opposite substrate stacked in sequence; the first array substrate comprises a first overlap portion overlapping with the first opposite substrate, a first extension portion extending from the first overlap portion, and the second array substrate comprises a second overlap portion overlapping with the second opposite substrate, a second extension portion extending from the second overlap portion; a side, facing the second extension portion, of the first extension portion comprises a first control IC, and a side, away from the first extension portion, of the second extension portion comprises a second control IC; and a space between the first and the second extension portions is filled with a heat dissipation component at least in an area where the first control IC is.

A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

A display substrate and a display panel are provided. The display substrate includes: a base including a front surface, a back surface and a side surface; a driving circuit layer disposed on the front surface; a back electrode disposed on the back surface; a side printed wire electrically connected to the driving circuit layer, the side printed wire extends to the back electrode from the side surface and is electrically connected to the back electrode, the side printed wire includes a wire top portion located on a side of the driving circuit layer facing away from the base; and a bonding adhesive layer disposed overlying the side of the driving circuit layer facing away from the base, the bonding adhesive layer is further in contact with and covers the wire top portion. The display substrate and the display panel can solve a problem of excessive height in a non-display area.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a substrate that has a device region and a ring region surrounding the device region, an interconnect structure disposed on the substrate, a first passivation layer disposed over the interconnect structure, a first contact via ring embedded in the first passivation layer, a first contact pad ring disposed on the first contact via ring and the first passivation layer, a second passivation layer disposed over the first contact pad ring, and a polymer layer disposed on a portion of the second passivation layer. The first contact via ring and the first contact pad ring completely surround the device region.