A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.

A semiconductor package according to the disclosure includes a terminal, a conductive pattern connected to the terminal, a barrier layer covering a top surface and a first side wall of the conductive pattern, an insulating layer surrounding the barrier layer, a protection layer covering a bottom surface of the insulating layer and a bottom surface of the barrier layer, a redistribution pattern connected to the barrier layer, a semiconductor chip electrically connected to the redistribution pattern, and a molding layer surrounding the semiconductor chip. A top surface of the protection layer includes a first portion contacting the conductive pattern, and a second portion contacting the barrier layer.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A substrate structure comprises a substrate having a first surface, a first electrode disposed on the first surface, a bump connected to the first electrode, and a protective member that covers the first surface and covers a portion of the bump. The protective member has an opening. The bump includes a portion exposed through the opening. The bump includes a first portion that is connected to the first electrode, and a second portion that is located farther from the first electrode than the first portion and is connected to the first portion. The bump has a constriction at a boundary between the first portion and the second portion. When viewed in a direction perpendicular to the first surface, a maximum diameter of the second portion is smaller than a maximum diameter of the first portion.

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.