The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

A display device includes a display substrate including a display area and a non-display area, a film substrate at least partially overlapping the non-display area of the display substrate, a driving chip located the film substrate, a film layer at a side surface of the display substrate, an adhesive layer between the film layer and a first surface of the film substrate, and a resin layer covering a second surface of the film substrate and a portion of an upper surface of the display substrate, wherein a portion of the resin layer and a portion of the film substrate are bent to the side surface of the display substrate.

A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.

A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.

Provided is a semiconductor chip, including: a semiconductor substrate; a thin film formed on the semiconductor substrate, the thin film having internal stress; and a semiconductor device formed on the semiconductor substrate that has the thin film formed thereon, wherein the semiconductor chip warps due to the internal stress of the thin film.

A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.

In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.