A semiconductor device includes a semiconductor substrate, a first anode electrode, and a second anode electrode. The first anode electrode is disposed on the semiconductor substrate. The second anode electrode is spaced from the first anode electrode on the semiconductor substrate around the first anode electrode. At least any of a first end of the first anode electrode on a second anode electrode side and a second end of the second anode electrode on a first anode electrode side is covered with a SInSiN film.

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.

A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

A micro-device structure includes a substrate having a substrate surface and a substrate contact disposed on or in the substrate surface, a cavity extending into the substrate from the substrate surface, a micro-device disposed in the cavity, the micro-device comprising a micro-device contact, a planarization layer disposed over at least a portion of the substrate, and an electrode disposed at least partially over or on the planarization layer and electrically connected to the micro-device contact.

The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.

A semiconductor device includes: a die pad having a top surface; a semiconductor chip provided on the top surface; a first solder provided between the top surface and the semiconductor chip, the first solder bonding the top surface and the semiconductor chip; a first metal film provided on the semiconductor chip; a first insulating film provided on the first metal film and having a first opening; a connector having a first end and a second end, the first end being provided on the first metal film in the first opening; a second metal film provided in the first opening, the second metal film having a plurality of second openings provided so as to surround a portion of the first metal film in contact with the first end, and the second metal film being provided between the first end of the connector and the portion of the first metal film; a plurality of second insulating films provided in direct contact with the first metal film in each of the second openings; and a second solder provided between the second metal film and the first end to bond the first end and the second metal film to each other.