A semiconductor device in which occurrence of peeling between a filling member and a metal terminal is suppressed is obtained. The semiconductor device includes: an insulating substrate having a front surface and a back surface, and having a semiconductor element joined to the front surface; a base plate joined to the back surface of insulating substrate; a case member surrounding insulating substrate; a filling member having an upper surface, covering insulating substrate, and filling a region surrounded by base plate and case member; and a metal member having a plate shape that leans toward an upper surface side of filling member inside filling member, has one end joined to the front surface of insulating substrate and another end separated from an inner wall of case member, and is exposed from the upper surface of filling member.

A first circuit board includes a positive output pin and a negative output pin of a power conversion circuit, each of which has a shape projecting from a second main surface. A second circuit board has a positive through via and a negative through via, each of which has a shape extending between a third main surface and a fourth main surface. The second main surface of the first circuit board and the third main surface of the second circuit board are physically in close contact with each other. The positive output pin is inserted through the positive through via to reach the fourth main surface. The negative output pin is inserted through the negative through via in such a manner as to reach the fourth main surface. The load receives a current supplied from the power conversion circuit through the positive output pin and the negative output pin.

A first circuit board includes a positive output pin and a negative output pin of a power conversion circuit, each of which has a shape projecting from a second main surface. A second circuit board has a positive through via and a negative through via, each of which has a shape extending between a third main surface and a fourth main surface. The second main surface of the first circuit board and the third main surface of the second circuit board are physically in close contact with each other. The positive output pin is inserted through the positive through via to reach the fourth main surface. The negative output pin is inserted through the negative through via in such a manner as to reach the fourth main surface. The load receives a current supplied from the power conversion circuit through the positive output pin and the negative output pin.

A circuit board module includes a first circuit board having a first main surface on which an electronic component that generates heat when the electronic component operates is mounted and a second main surface, a second circuit board having a third main surface on which the first circuit board is mounted and a fourth main surface, and a first thermally-conductive sheet between the first circuit board and the second circuit board. The first circuit board is mounted such that the second main surface faces the third main surface. The first circuit board includes thermally-conductive vias that extend between the first and second main surfaces, the vias being densely distributed in a region near a mounting terminal of the electronic component, filled with a thermally-conductive member, and physically in contact with the first thermally-conductive sheet that covers the third main surface of the second circuit board.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

Structures and formation methods of a chip package structure are provided. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion (CTE) material layer with a CTE that is substantially equal to or greater than 9 ppm/° C. The organic material layer is in direct contact with the upper surface of the semiconductor die, and the overlying high CTE material layer covers the upper surface of the semiconductor die.

The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.

A package assembly includes an interposer module on a package substrate, a thermal interface material (TIM) film on the interposer module, and a package lid that includes a plate portion on the TIM film and a step region projecting away from the plate portion and located over the TIM film and over an edge region of the interposer module.

A package assembly includes an interposer module on a package substrate, a thermal interface material (TIM) film on the interposer module, and a package lid that includes a plate portion on the TIM film and a step region projecting away from the plate portion and located over the TIM film and over an edge region of the interposer module.

A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.