A semiconductor package includes a semiconductor die, a thermal conductive through via and a conductive paste. The thermal conductive through via is electrically insulated from the semiconductor die. The conductive paste is disposed over the semiconductor die, wherein the thermal conductive through via is thermally coupled to the semiconductor die through the conductive paste.

Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is connected to a third power terminal.

A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element is connected to a third power terminal.

Improved heat sinking of electronic and/or photonic integrated circuit chips is provided by including thermal-only contacts on unused parts of the chip. The resulting chip can be bonded to a cold plate with a process that ensures that only the thermal contacts of the chip touch the cold plate, thereby avoiding problems caused by the cold plate creating electrical shorts of the chip. For example, the thermal contacts can be higher features than any electrical features on that side of the chip. This approach is expected to be especially useful for applications requiring low temperature operation (e.g., operation at 100K or less, preferably operation at 10 K or less).

The waterproof casing has a housing and a grommet. The grommet is disposed in a hole of the housing. The grommet has a body, a flange, and a lip. The flange extends radially outward from the body. The lip protrudes from an outer peripheral part of the body and extends in a circumferential direction. The lip has a high compression portion in contact with a wall surface of the hole and a low compression portion adjacent to the high compression portion at a further side from the flange. The low compression portion has a lower compressed state than the high compression portion. The housing has a recess to allow the low compression portion to escape radially outward.

A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.