A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

Embodiments of the disclosure provide a method to form an air gap structure. An opening is formed in a first dielectric layer between adjacent conductors. A first dielectric layer is formed over the opening to fill a first portion of the opening. A remainder of the opening is free of the first dielectric layer. A second dielectric layer is formed on a top surface of the first dielectric layer, with a remainder of the opening unfilled. The second dielectric layer is devoid of wiring. The remainder of the opening below the second dielectric layer defines an air gap structure. A wiring layer is formed above the air gap structure.

The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. The semiconductor device structure includes a support layer formed over the air gap structure. A bottom surface of the support layer is in direct contact with the air gap structure, and the bottom surface of the support layer is lower than a top surface of the first conductive layer and higher than a bottom surface of the first conductive layer.

A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

A semiconductor device includes: a lower electrode; a first dielectric layer provided on the lower electrode; a first upper electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper electrode; a second upper electrode provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer provided on the second upper electrode; and a third upper electrode provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor between the lower electrode and the first upper electrode, a second capacitor between the first upper electrode and the second upper electrode, and a third capacitor between the second upper electrode and the third upper electrode are connected in parallel with each other.

In accordance with the disclosure, one or both semiconductor dies in a face-to-face arrangement may include a probe pad layer formed on a face of the die to allow the die to be individually tested prior to assembly of the dies. Thus, faulty dies may be discarded individually so they are not included in a composite semiconductor device, thereby increasing device yields. The probe pad layer also allows dies to be matched so that a composite semiconductor device achieves desired performance, which may further increase device yields. In some embodiments, the probe pads of the probe pad layer formed on the face of the die may be used to individually test the die, and may remain inactive, or inert, during operation of the composite semiconductor device.

An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes first and second interconnect substrates on a same surface level, first and second integrated circuit (IC) chips disposed on the first and second interconnect substrates, respectively, an IC chip coupler disposed on the first and second interconnect substrates and configured to provide a signal transmission path between the first and second IC chips, and a redistribution structure disposed on the first and second IC chips and the IC chip coupler. The IC chip coupler includes a first coupler region that overlaps with the first interconnect substrate, a second coupler region that overlaps with the second interconnect substrate, a third coupler region that overlaps with a space between the first and second interconnect substrates, and an interconnect structure with conductive lines and conductive vias.