A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the present disclosure includes: providing a substrate, the substrate being provided with first trenches arranged in a same direction; forming protective layers on side walls of the first trenches; forming second trenches at bottoms of the first trenches, the second trenches being wider than the first trenches; forming first spacers on side walls of the second trenches to reduce opening sizes of the second trenches; filling the first trenches and the second trenches to form second spacers, and forming voids in the second trenches; forming third trenches in the substrate, the third trenches being perpendicular to the first trenches; and forming bit lines in the third trenches.

An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.

A semiconductor device including a plurality of wirings and an insulating space is described. The insulating space is disposed between adjacent wirings of the plurality of wirings. An insulating material surrounds the insulating space. The insulating space is filled with air at a pressure no more than an atmospheric pressure.

A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device (1) including: a first inter-wiring insulating layer (120) that is provided on a substrate (100) and includes a recess on a side opposite to the substrate; a first wiring layer (130) that is provided inside the recess in the first inter-wiring insulating layer; a sealing film (140) that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer; a second inter-wiring insulating layer (220) that is provided on the first inter-wiring insulating layer to cover the recess; and a gap (150) that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.

An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

The present disclosure provides a semiconductor structure, including: a plurality of metal layers and a substrate, wherein the plurality of metal layers include a first metal layer, a second metal layer, and a third metal layer; a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers; the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first metal layer.

A semiconductor structure includes a plurality of metal layers and a substrate. The plurality of metal layers are provided with a plurality of virtual metal blocks and at least one signal line. A first projection of a first virtual metal block on the substrate is a polygon, the first projection has a plurality of effective sides opposite to a second projection of a target signal line on the substrate, and differences from the plurality of effective sides of the first projection to a straight line where the second projection is located are different, and the first virtual metal block is a virtual metal block, closest to the target signal line, on the target metal layer, and the target metal layer is a metal layer where the target signal line is located.