According to one embodiment, an isolator includes first and second conductive members, and first second, and third insulating members. The first conductive member includes first, second, and third partial regions. The third partial region is between the first and second partial regions. The second conductive member is electrically connected to the first conductive member. The second conductive member includes fourth and fifth partial regions. The fourth partial region is between the third and fifth partial regions. The first insulating member includes first and second insulating regions. The fifth partial region is between the first and second insulating regions. The second insulating member includes third and fourth insulating regions. The fourth partial region is between the third and fourth insulating regions. The third insulating member includes first and second portions.

A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the third inductor portion is electrically connected to a second end portion of the second inductor portion.

A module includes a substrate, metal layers and insulating layers laminated on the substrate, a bottom winding made of a metal directly contacting a first metal layer or a second metal layer, a first insulating layer on the bottom winding, a core on the first insulating layer, a second insulating layer on the core, a top winding made of the metal that is located on the core and a portion of the second insulating layer and that directly contacts the first metal layer or the second metal layer, and a third insulating layer on the top winding, electronic components that are located on the third insulating layer, where primary and secondary windings of the transformer are defined by portions of the bottom winding and the top winding and are located on opposite sides of the core from each other.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package leadframe having a first die pad and a second die pad separated from the first die pad. A first semiconductor die is attached to the first die pad of the package leadframe. A second semiconductor die is attached to the second die pad of the package leadframe. A communication device is attached over the second semiconductor die. The communication device is configured to communicate wirelessly with the second semiconductor die.

A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.