A fuse structure and a manufacturing method thereof are provided. The fuse structure includes: a substrate; an active region positioned above the substrate; a fuse gate structure surrounding a circumferential outer surface of the active region and electrically connected to a first power source; and a control gate structure surrounding a circumferential outer surface of the fuse gate structure and electrically connected to a second power source. A voltage of the first power source is greater than that of the second power source.

A fuse structure and a method for manufacturing the same are provided. The fuse structure includes a substrate; a fin, located on the substrate and including a first fin region; and a gate stack structure, surrounding the top and side walls of the first fin region. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, the second gate stack covers the first gate stack. The first gate stack is configured to receive a first gate voltage, the second gate stack is configured to receive a second gate voltage, and the first gate voltage is greater than the second gate voltage. The fuse structure reduces the area of the fuse unit and increase the integration level of the fuse circuit.

A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.

A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.

A memory device is disclosed. The memory device includes a transistor and a resistor electrically connected to the transistor. The transistor and the resistor form a first one-time programmable (OTP) memory cell. The resistor includes a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state.

An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.