The present disclosure provides a semiconductor package capable of improving performance and reliability. The semiconductor package of the present disclosure includes a first device and a second device that are electrically connected to each other, the first device includes a substrate, a first pad formed on an upper side of the substrate, and a passivation film formed on the upper side of the substrate and formed to surround the first pad, the second device includes a second pad placed to face the first pad, and the first pad has a center pad having a first elastic modulus and an edge pad having a second elastic modulus smaller than the first elastic modulus, the edge pad formed to surround the center pad and to contact the passivation film.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

An imaging device includes a photoelectric conversion film and an electrode. The photoelectric conversion film converts light to charge. The electrode collects the charge. The electrode includes two or more layers. The two or more layers include a first layer containing tantalum nitride. An uppermost layer among the two or more layers contains a metal nitride.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. A semiconductor device includes a substrate, a cell array structure including a plurality of electrodes stacked on the substrate, a vertical channel structure that penetrates the cell array structure and is connected to the substrate, a conductive pad in an upper portion of the vertical channel structure, an interlayer insulating layer on the cell array structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a first stress release layer between the cell array structure and the bit line on a top surface of the interlayer insulating layer. The first stress release layer includes organosilicon polymer, and a carbon concentration of the first stress release layer is higher than that of the interlayer insulating layer.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.

Provided are a solid-state imaging apparatus, a method for manufacturing a solid-state imaging apparatus, and an electronic apparatus equipped with a solid-state imaging apparatus that can reduce the size of a semiconductor chip in such a way that one semiconductor substrate having a logic circuit controls two sensors. Provided is a solid-state imaging apparatus including a first sensor, a first semiconductor substrate having a memory, a second semiconductor substrate having a logic circuit, and a second sensor, in which the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.