An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.

A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer interconnects the IC device with a power source. A passive inductive component of the IVR circuit is deployed upon a surface of the IC device or the interposer. The inductive component has a magnetic core and a winding (e.g., wire-bond), wound about the magnetic core.

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

An integrated circuit includes a first terminal that is connected to a first end of a first capacitor, the first capacitor being included in a resonant circuit, a second terminal that is connected to a second end of the first capacitor, a plurality of second capacitors connected in parallel between the first and second terminals, and a control circuit which, in operation, changes a capacitance of each of the second capacitors. An electronic pen includes the integrated circuit and a first capacitor having a capacitance that varies based on pressure applied to a nib of the electronic pen.

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.

An inductor device may include a first electrically conductive path and a second electrically conductive path. The first electrically conductive path may extend from a first terminal of the inductor device to a second terminal of the inductor device. The second electrically conductive path may extend from a third terminal of the inductor device to a fourth terminal of the inductor device. The second electrically conductive path may be magnetically coupled to the first electrically conductive path. Each of the third terminal and the fourth terminal may be offset with respect to a virtual axis extending through the first terminal and the second terminal.

An inductor package is described comprising a mold interconnection substrate having an embedded spiral coil inductor, a fan-out redistribution layer connected to the spiral coil inductor by a copper post wiring structure, a ferrite toroid coil in between the copper posts, and a semiconductor die mounted on the mold interconnection substrate and connected to the fan-out redistribution layer.