A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

A surface mount component is disclosed including an electrically insulating beam that is thermally conductive. The electrically insulating beam has a first end and a second end that is opposite the first end. The surface mount component includes a thin-film component formed on the electrically insulating beam adjacent the first end of the electrically insulating beam. A heat sink terminal is formed on the electrically insulating beam adjacent a second end of the electrically insulating beam. In some embodiments, the thin-film component has an area power capacity of greater than about 0.17 W/mm.sup.2 at about 28 GHz.

In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Provided is a resistor structure of a series resistor of an Electro-Static Discharge (ESD) device. A poly resistor is divided into N small parts, and each small part is connected to an upper-part metal layer through a respectively corresponding Contact and Via. The Contact and Via corresponding to each small part and the connected upper-part metal layer form an independent unit. A metal aluminum material is adopted for the Via and the upper-part metal layer. The metal aluminum material or an aluminum alloy material is adopted for the Contact. A heat capacity characteristic of metal aluminum is utilized, and an existing structure is ingeniously utilized, so that the resistor may be prevented from being damaged by heating caused by the same ESD current, and meanwhile, an overall size of a circuit where the ESD device is located is greatly reduced.

An electronic component is provided that includes multiple conductive terminals and an insulator integrated with the conductive terminals. A leg part possessed by one of the conductive terminals and a leg part possessed by another one of the conductive terminals are disposed so as to vertically overlap each other. The leg part possessed by one of the conductive terminals and the leg part possessed by another one of the conductive terminals have different lengths, and the tip of the shorter leg part of the two is covered by a thick part of the insulator.

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

A noise reduction circuit is connected between at least one line of an input line and an output line of a DC-DC converter, a ground, and a ground terminal of a switching control IC included in the DC-DC converter. The noise reduction circuit includes a first capacitor connected between the at least one line and the ground terminal, a second capacitor connected between the at least one line and the ground, and an inductor connected between the ground terminal and the ground.

Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.