A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

A light emitting apparatus including: one or a plurality of light emitting devices each having a plurality of electrodes and each emitting light from the upper surface of the light emitting device; a plurality of terminal electrodes provided on the lower side of the light emitting devices in a positional relation with the light emitting devices and electrically connected to the electrodes of the light emitting devices; a first metal line brought into contact with the upper surfaces of the light emitting devices and one of the terminal electrodes, provided at a location separated away from side surfaces of the light emitting devices and created in a film creation process; and an insulator in which the light emitting devices and the first metal line are embedded.

A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching element are fixed on a second substrate. An upper arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. The lower arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element.

An electronic power module, including at least one semiconductor component, which is arranged on a support, as well as a cooling element, which is in thermal contact with the semiconductor component, wherein the support includes a semiconductor material and, at the same time, serves as a cooling element.

A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

A power semiconductor device includes a first power semiconductor element, a second power semiconductor element, a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The power semiconductor device also includes a DC positive terminal, a DC negative terminal, an AC terminal, and a sealing member that integrally seals the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate. Each of the DC positive terminal, the DC negative terminal, and the AC terminal has a cut section formed by cutting a tie bar that integrally couples the DC positive terminal, the DC negative terminal, and the AC terminal.

A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape.