A FinFET includes at least two fins arranged in parallel, a plurality of valid gates, and a first dummy polycrystalline silicon. The at least two fins extend in a first direction, and the plurality of valid gates and the first dummy polycrystalline silicon extend in a second direction and cover surfaces of the at least two fins. The first dummy polycrystalline silicon is located on one side of the plurality of valid gates, and fins on both sides of each of the plurality of valid gates are respectively a source terminal and a drain terminal of the FinFET. The plurality of valid gates is coupled to a gate terminal of the FinFET. The first dummy polycrystalline silicon is coupled between the gate terminal of the FinFET and a resistor potential terminal.

Systems and methods for RF hazard protection are provided. In one embodiment, a RF protection coupler comprises: a first port to couple to an output of an RF source circuit; a second port to couple to an external RF load; a source side and load side RF switches, wherein the source side RF switch and the load side RF switch are each switch between a first and second states in response to a detected matting. In the first state the source and load side RF switches establish an electrical path between the first and second ports. In the second state: the source side RF switch couples the first port to an impedance load that is impedance matched to the output of the RF source circuit; the load side RF switch couples the second port to an electrical ground; and a gap between the switches electrically isolates the ports.

A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

A semiconductor photodiode. The semiconductor photodiode including: an input waveguide, arranged to receive an optical signal at a first port and provide the optical signal from the second port; a photodiode waveguide, arranged to receive the optical signal from the second port of the input waveguide, and at least partially convert the optical signal into an electrical signal; and an electro-static defence component, located adjacent to the photodiode waveguide. The electro-static defence component and the photodiode waveguide are electrically connected in parallel.

A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.

A layout structure of an anti-fuse array at least includes an array circuit area and a functional circuit area. The array circuit area is electrically connected with the functional circuit area. The functional circuit area is located on at least one side of the array circuit area, and at least one side of the array circuit area is located on an edge of the layout structure. The array circuit area includes an anti-fuse array composed of anti-fuse cells, and the array circuit area is configured to provide the anti-fuse cells under different column addresses to the functional circuit area. The functional circuit area is configured to fuse the anti-fuse cells under the different column addresses.

The present disclosure provides an electronic device including a driving circuit substrate, a plurality of chips, and a passivation layer. The driving circuit substrate includes a plurality of active elements. The chips are disposed on the driving circuit substrate and electrically connected to the driving circuit substrate. The passivation layer covers the plurality of chips and the driving circuit substrate. The passivation layer has a first part on one of the plurality of chips and a second part on a part of the driving circuit substrate, the second part is not overlapped with the plurality of chips, and a first thickness of the first part is less than a second thickness of the second part. The first space between adjacent two of the plurality of chips is different from a second space between another adjacent two of the plurality of chips.

Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

A 3D integrated circuit includes a substrate, a first layer on top of the substrate, and a second layer on top of the first layer. The first layer includes a first chip, and a first network bridge formed at a first side of the first chip. The second layer includes a second chip, and a second network bridge formed at a first side of the second chip. The first chip and the first network bridge are coupled to the substrate through bumps. The second chip is coupled to the first chip and the first network bridge through bumps. The second network bridge is coupled to the first network bridge through bumps. The first network bridge and the second network bridge each include a network switch for controlling data transfer and/or power distribution.

Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.