A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.

A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures. The high-density capacitor has a capacitance that is proportional to the volume of the capacitor.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

A method according to an embodiment is for forming a capacitor structure on a wafer. A first capacitor is formed on a first side of a wafer, and a second capacitor is formed on a second side of the wafer. The capacitor structure includes the first capacitor and the second capacitor. A trench capacitor is fabricated at both ends of an interposer, which can increase capacitance, and greatly improve the stability of the supplied power.

An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.