Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.

An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.

A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.