A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, a ferroelectric composite layer disposed between the first electrode and the second electrode, and a first insulating layer disposed on one side of the ferroelectric composite layer.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed to advanced integrated circuit structure fabrication and, in particular, integrated circuits with high dielectric constant (HiK) interfacial layering between an electrode and a ferroelectric (FE) or anti-ferroelectric (AFE) layer. Other embodiments may be disclosed or claimed.

A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.

A capacitor includes: a bottom electrode; a top electrode; and a hybrid dielectric layer including at least one nanosheet material disposed between the bottom electrode and the top electrode.

Provided are a capacitor, an electronic device including the same, and a method of manufacturing the same, the capacitor including a first thin-film electrode layer; a second thin-film electrode layer; a dielectric layer between the first thin-film electrode layer and the second thin-film electrode layer; and an interlayer between the dielectric and at least one of the first thin-film electrode layer or the second thin-film electrode layer, the interlayer including a same crystal structure type as and a different composition from at least one of the first thin film electrode layer, the second thin film electrode layer, or the dielectric layer, the interlayer including at least one of a anionized layer or a neutral layer.

An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n≥1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m≥n+1.

Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

A capacitor including a lower electrode; an upper electrode apart from the lower electrode; and a between the lower electrode and the upper electrode, the dielectric including a dielectric layer including TiO.sub.2, and a leakage current reducing layer including GeO.sub.2 in the dielectric layer. Due to the leakage current reducing layer, a leakage current is effectively reduced while a decrease in the dielectric constant of the dielectric thin-film is small.