An electrostatic discharge (ESD) protection device, incudes an N-type well and a P-type well formed in a semiconductor substrate; a first N-type diffusion region and a first P-type diffusion region formed in the N-type well, separated by a first separation film, and each connected to an Anode terminal; a second N-type diffusion region and a second P-type diffusion region formed in the P-type well, separated by a second separation film, and each connected to a Cathode terminal; a P-type floating region, formed in the P-type well, spaced apart from the second N-type diffusion region and the second P-type diffusion region; and a non-sal layer covering the P-type floating region.

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of second conductivity type provided on the first semiconductor layer; a second electrode provided on the second semiconductor layer; a first trench reaching the first semiconductor layer from the second semiconductor layer; a first semiconductor region provided in the second semiconductor layer, the first semiconductor region being in contact with the first trench and the first semiconductor region having a higher concentration of impurities of second conductivity type than the second semiconductor layer; and a first insulating film provided in the second semiconductor layer and the first insulating film being in contact with the first semiconductor region.

A semiconductor device includes: a first semiconductor layer located in a diode region, the first semiconductor layer including a plurality of first semiconductor regions and a plurality of second semiconductor regions alternately arranged in a first direction; a second semiconductor layer located in the IGBT region; and a third semiconductor layer located on the first semiconductor layer in the diode region, an impurity concentration of the third semiconductor layer having a maximum at a first position in a second direction, an impurity concentration of the first semiconductor region having a maximum at a second position in the second direction, a third position being separated from the upper surface of the first electrode by a length that is 3 times a distance between the second position and a lower end of the third semiconductor layer, the first position being the same as or lower than the third position.

A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.

A semiconductor device includes an insulator layer and a semiconductor layer formed on the insulator layer. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type, and a lightly doped extension region of the first conductivity type separating the first region and the second region along a lateral x-axis. A dielectric structure laterally surrounds the semiconductor layer. At least one of the first region and the lightly doped extension region is formed at a distance to the dielectric structure along a lateral y-axis orthogonal to the x-axis. Along the x-axis and between the second region and the first region, a lateral extension of the semiconductor layer along the y-axis increases with increasing distance to the second region.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. The method includes implanting protons through the second surface into the semiconductor body. The method further includes implanting ions through the second surface into the semiconductor body. The ions are ions of a non-doping element having an atomic number of at least 9. Thereafter, the method further includes processing the semiconductor body by thermal annealing.

A semiconductor device including a semiconductor substrate, first and second transistor sections and a diode section provided on the substrate, is provided. The diode section is arranged to be adjacent to and sandwiched between the first and second transistor sections in a predetermined arrangement direction. The diode section includes a drift region; a base region above the drift region; first cathode regions and second cathode regions below the drift region. The first and second transistor sections each include a collector region. The first cathode regions are provided continuously between the collector regions of the first and second transistor sections. One end and another end of the first cathode regions in the arrangement direction are in contact with the collector regions of the first and second transistor sections, respectively. The first and second cathode regions are in contact with each other and alternating in a direction orthogonal to the arrangement direction.

A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Disclosed is a field effect transistor (FET) and a method for manufacturing the same, the FET comprises: a substrate, a first well region located on the substrate, a second well region, a body contact region, a source region, a drain region and a gate conductor. The body contact region, the source region and the drain region are located in the first well region, the doping concentration of the second well region is higher than that of the first well region. A parasitic bipolar junction transistor (BJT) is located in the field effect transistor, current flowing through the BJT is controlled by adjusting doping concentration or area of the second well region. The second well region is formed in the first well region, so that the holding voltage of the FET is improved, and finally effect on the FET caused by the current flowing through the BJT can be weakened.