A cascode transistor device includes a semiconductor substrate, and a first and a second compound semiconductor transistors. The first compound semiconductor transistor includes a first n-type doping layer, a first p-type doping layer and a second n-type doping layer sequentially disposed on the semiconductor substrate. The second compound semiconductor transistor includes a third n-type doping layer, a second p-type doping layer and a fourth n-type doping layer sequentially disposed on the second n-type doping layer. Each of these doping layers is formed with an exposed metal contact. The exposed metal contact on the second n-type doping layer is electrically connected to the exposed metal contact on the third n-type doping layer.

Provided is a semiconductor device in which a first anode layer and a first contact layer are provided on a first main surface side in a diode region, and in which a second anode layer and a second contact layer are provided on the first main surface side in a boundary region. A concentration of impurities of a second conductive type of the second anode layer is lower than a concentration of impurities of the second conductive type of the first anode layer, or an occupied area ratio of the second contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the boundary region is smaller than an occupied area ratio of the first contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the diode region.

A transient voltage suppression device including a substrate of a first conductivity type, a first well of a second conductivity type, a first anode, a first cathode, and a first trigger node is provided. The first well is disposed in the substrate. The first anode is disposed in the substrate outside the first well and includes a second doped region of the second conductivity type and a third doped region of the first conductivity type disposed between the second doped region and the first doped region. The first trigger node is disposed between the first anode and the first cathode, and includes a fourth region of the first conductivity type disposed in the substrate and a fifth doped region of the second conductivity type at least partially disposed in the first well and disposed between the fourth doped region and the third doped region.

A semiconductor device includes: an inner region including a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region; and well regions having a higher doping concentration than that of the base region, provided from the upper surface of the semiconductor substrate to a depth position greater than a lower end of the base region, and arranged with the inner region interposed therebetween at the upper surface of the semiconductor substrate. The inner region includes a longitudinal side in a predetermined longitudinal direction at the upper surface of the semiconductor substrate and a plurality of trench portions which extend from the upper surface of the semiconductor substrate to the drift region. At least one of the trench portions is separated into two or more partial trenches in the longitudinal direction, in a region which does not overlap the well regions.

A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

An electro-static discharge (ESD) protection device includes a first well region and a second well region disposed to contact each other, a first diffusion region and a second diffusion region disposed in the first well region spaced apart from each other, a third diffusion region and a fourth diffusion region disposed in the second well region spaced apart from each other, a resistive pattern coupled to the first diffusion region through a first contact plug, a first electrode coupled to the second diffusion region through a second contact plug and electrically coupled to the resistive pattern, and a second electrode coupled to the third diffusion region through a third contact plug and coupled to the fourth diffusion region through a fourth contact plug.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 μm and less than 200 μm. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm.

A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.

A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a second electrode. The fourth semiconductor layer is located in a second region on the first semiconductor layer. The fourth semiconductor layer is separated from the second semiconductor layer with a portion of the first semiconductor layer interposed. An impurity concentration of the fourth semiconductor layer is greater than an impurity concentration of the first semiconductor layer and less than an impurity concentration of the second semiconductor layer.