In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

A high electron mobility transistor (HEMT) includes an active region, in which a channel is formed, and a field region surrounding the active region. The HEMT may include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate may protrude from the active region to the field region on the barrier layer. The gate may include a first gate and a second gate. The first gate may be in the active region and the second gate may be in the boundary region between the active region and the field region. A work function of the second gate may be different from a work function of the first gate.

A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

A transistor device ac includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, a source contact and a drain contact on the barrier layer, and a gate contact on the barrier layer between source contact and the drain contact. The device further includes a plurality of selective modified access regions at an upper surface of the barrier layer opposite the channel layer. The selective modified access regions include a material having a lower surface barrier height than the barrier layer, and the plurality of selective modified access regions are spaced apart on the barrier layer along a length of the gate contact.

A semiconductor device includes a substrate having a first surface and a second surface, the second surface being opposite to the first surface, the substrate having an opening formed from the first surface toward the second surface; a semiconductor device layer having a third surface facing the second surface; and a heat transfer member disposed in the opening, the heat transfer member being configured to transfer heat generated by the semiconductor device layer to the first surface, wherein the heat transfer member includes a diamond layer and a metal layer, the diamond layer covering a bottom surface and an inner wall surface of the opening, and the metal layer being disposed on the diamond layer.

A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.

Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO.sub.3.

Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.