An electronic or optoelectronic device includes: (1) a layer of a first material; and (2) a layer of a second material disposed on the layer of the first material, wherein the first material is different from the second material, and the layer of the first material is spaced from the layer of the second material by a gap.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.

A method of manufacturing a semiconductor device is described. The method includes providing a parent substrate including a substrate portion of a first conductivity type. The method further includes forming an absorption layer in the parent substrate by an ion implantation process of an element through a first surface of the parent substrate. The method further includes forming a semiconductor layer structure on the first surface of the parent substrate. The method further includes splitting the parent substrate along a splitting section through a detachment layer. The detachment layer is arranged between the absorption layer and a second surface of the parent substrate at a vertical distance to the absorption layer.

A method of forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device includes: providing a semiconductor body; implanting a dopant to form a doped region in the semiconductor body; providing, above the doped region, a mask layer having a first section and a second section, the first section having has a first thickness along a vertical direction and the second section having a second thickness along the vertical direction, the second thickness being different from the first thickness; and subjecting the doped region and both mask sections to a laser thermal annealing, LTA, processing step.

Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a gate region, a source region and a drain region; a source region N-type ion heavily-doped layer located in the source region; a drain region N-type ion heavily-doped layer located in the drain region; a gate electrode located in the gate region; a source electrode located on the source region N-type ion heavily-doped layer; and a drain electrode located on the drain region N-type ion heavily-doped layer.

An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.