A device is provided that comprises a first layer deposited onto a second layer. The second layer comprises a lightly doped n-type or p-type semiconductor drift layer, and the first layer comprises a high-k material with a dielectric constant that is at least two times higher than the value of the second layer. A metal Schottky contact is formed on the first layer and a metal ohmic contact is formed on the second layer. Under reverse bias, the dielectric constant discontinuity leads to a very low electric field in the second layer, while the electron barrier created by the first layer stays almost flat. Under forward bias, electrons flow through the first layer, into the metal ohmic contact. For small values of conduction band offset or valence band offset between the first layer and the second layer, the device is expected to support efficient electron or hole transport.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.

Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has a plurality of trenches formed in a position overlapping the anode electrode in a plan view. Among the plurality of trenches, a trench positioned at the end portion has a selectively increased width. Thus, the curvature radius of the bottom portion of the trench is increased, or an edge part constituted by the bottom portion as viewed in a cross section is divided into two parts. As a result, an electric field to be applied to the bottom portion of the trench positioned at the end portion is mitigated, making dielectric breakdown less likely to occur.

An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

A voltage-sustaining layer for semiconductors, including: a source region heavily doped with a first conductive type, a drain region heavily doped with a second conductivity type, a first region doped with the first conductivity type, a second region doped with the second conductivity type, N first oxide layers and K second oxide layers. The second region is located above the second drain region. The first region is located above the drain region and at a side of the second region. The source region is located above the first region and the second region. The first oxide layers are located at a side in the second region close to the source region. The second oxide layers are located at a side in the first region close to the drain region.

The present application belongs to the technical field of semiconductor power devices and provides a semiconductor power device. The semiconductor power device includes an n-shaped substrate, an n-shaped epitaxial layer positioned on the n-shaped substrate, and at least three grooves recessed inside the n-shaped epitaxial layer, where a portion of the n-shaped epitaxial layer between two adjacent grooves of the at least three grooves is a mesa structure, an upper part of the mesa structure is provided with a p-shaped body region, and an n-shaped source region is provided inside the p-shaped body region. The mesa structure includes at least one mesa structure with a lower width being a first width and at least one mesa structure with a lower width being a second width, and the second width is greater than the first width.

A first nitride semiconductor layer and a second nitride semiconductor layer are laminated in a first direction. The first and second nitride semiconductor layers form a heterojunction, and a two-dimensional carrier gas is induced in the first nitride semiconductor layer. A drain electrode is opposite to a source electrode via gate electrode in a third direction. The source electrode and the drain electrode conduct with the first nitride semiconductor layer. The first and second nitride semiconductor layers form a Schottky junction with the gate electrode. A first layer is located between the gate electrode and the drain electrode in the third direction and is in contact with the gate electrode, and is in contact with the second nitride semiconductor layer in a second direction. The first layer suppresses induction of the two-dimensional carrier gas in the first nitride semiconductor layer opposite to the first layer in the first direction.