Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.

Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 μm. The FET device can include one or more substrate contact features as well.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).

An embodiment of a semiconductor device includes an MOS transistor having a gate that is formed to have a gate width that extends vertically into the semiconductor material in which the MOS transistor is formed. A gate length of the MOS transistor is formed to traverse substantially laterally and substantially parallel to a surface of the semiconductor material in which the MOS transistor is formed.

A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of tip-to-side shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

A method for forming a semiconductor device includes incorporating dopants of a first conductivity type into a nearby body region portion of a semiconductor substrate having a base doping of the first conductivity type. The incorporation of the dopants of the first conductivity type is masked by a mask structure at at least part of an edge region of the semiconductor substrate. The method further includes forming a body region of a transistor structure of a second conductivity type in the semiconductor substrate. The nearby body region portion of the semiconductor substrate is located adjacent to the body region of the transistor structure.

The disclosure relates to a controller (606) for a switched mode power supply, SMPS (600), comprising: a switch toggling unit (670) having a first switching mode and a second switching mode, wherein the first switching mode is a continuous conduction mode or a boundary conduction mode and the second conduction mode is a discontinuous conduction mode; and a switch mode selector (676) configured to set the switching mode of the switch toggling unit (670) in accordance with a current in an inductor (602) of the SMPS (600).

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.