A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

A display panel includes a base layer, a signal line which is disposed on the base layer and includes a first layer including aluminum and a second layer disposed directly on the first layer and consisting of niobium, a first thin film transistor connected to the signal line, a second thin film transistor disposed on the base layer, a capacitor electrically connected to the second thin film transistor, and a light emitting element electrically connected to the second thin film transistor.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

The present disclosure is related to an array substrate. The array substrate may include a base substrate and a pixel defining layer on the base substrate. The pixel defining layer may include a plurality of thickness thinning regions. The thickness thinning regions may have a smaller height than other areas of the pixel define layer on the base substrate. The plurality of the thickness thinning regions may be configured to guide flow of fillers to form an encapsulating layer on the pixel defining layer.

An organic electroluminescence device including: an anode, a cathode, and at least one emitting layer between the cathode and the anode, wherein the emitting layer contains a first host material, a second host material, and a dopant material, the first host material is a compound having at least one deuterium atom, and the emitting layer contains the first host material in the proportion of 1% by mass or more.

A display panel having a hole running through the display panel includes: a base substrate; a plurality of light-emitting devices, organic light-emitting functional layers of the light-emitting devices extending to an edge region; an isolation spacer located on the base substrate within the edge region and which are annular structures that surround the hole, the organic light-emitting functional layers are interrupted at the isolation spacer; and an encapsulation layer covering the plurality of light-emitting devices. An inorganic layer in the encapsulation layer extends to the edge region and covers the isolation spacer and the organic light-emitting functional layers. The isolation spacer includes: an inner layer structure and an outer layer structure. The side of the inner layer structure away from the base substrate is provided with a groove-shaped structure, and the outer layer structure includes a through hole.

A display substrate, a preparation method therefor, and a display apparatus. The display substrate comprises: a plurality of pixel island areas that are separated from one another, a plurality of hole areas, and a connection bridge area that connects the plurality of pixel island areas. The hole areas each comprise a base substrate and an encapsulation layer, the base substrate is provided with an aperture, a barrier structure is provided on the side of the base substrate close to the aperture, and the encapsulation layer covers the side of the base substrate close to the aperture.