Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.

A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.

A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.

Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.