Provided is a thin film transistor array substrate, including a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor pattern formed on the gate insulating layer and including a channel region overlapping the gate electrode, a source electrode and a drain electrode formed on the semiconductor pattern and facing each other with a first opening exposing the channel region therebetween, a first protective layer formed on the gate insulating layer to cover the source electrode, the drain electrode and the semiconductor pattern and a metal oxide layer formed along a surface of the first protective layer.

An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench formed in penetration through the source region, a base region, a termination trench formed around the active trench, a gate insulating film formed on a bottom surface, a side surface of the active trench, a gate electrode embedded and formed in the active trench with the gate insulating film interposed therebetween, a protective diffusion layer of a second conductivity type formed in a lower portion of the active trench and a part of a lower portion of the termination trench and having a first impurity concentration, and a termination diffusion layer of the second conductivity type formed on an outside of the protective diffusion layer in the lower portion of the termination trench and having a second impurity concentration lower than the first impurity concentration.

A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.

A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound.

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

An oscillator oscillating a tera hertz wave includes a negative resistive element including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, with a first conductor, a second conductor, and a dielectric disposed between the first conductor and the second conductor constitutes a resonator, wherein the negative resistive element is disposed between the first conductor and the second conductor, and a layer with a higher resistivity than the first semiconductor layer or the second semiconductor layer, or an amorphous layer is disposed between the negative resistive element and the dielectric.

A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

A field effect transistor includes a III-Nitride channel layer, a III-Nitride doped cap layer on the channel layer, a source electrode in contact with the III-Nitride cap layer, a drain electrode in contact with the III-Nitride cap layer, a gate electrode located between the source and the drain electrodes, and a gate dielectric layer between the gate electrode and the III-Nitride undoped channel layer, wherein the cap layer is doped to provide mobile holes, and wherein the gate dielectric layer comprises a layer of AlN in contact with the channel layer.