A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.

A signal transmission device relating to a technique disclosed in the specification of the present application includes: an isolation transformer; an input-side circuit connected to an input side of the isolation transformer; and an output-side circuit connected to an output side of the isolation transformer. The output-side circuit includes a first differential circuit having a first input and a second input connected to the first terminal and the second terminal respectively. A reference potential of the first differential circuit is connected to the second terminal.

A Schottky barrier diode according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the wile terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal.

A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the wile terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal.

A semiconductor device includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n− type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n− type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.

A split in a dicing street in a semiconductor film is prevented. A semiconductor device includes: a first dicing street passing between a plurality of element regions on which a plurality of protective films are formed one-to-one, the first dicing street extending along a first axis; a second dicing street passing between the plurality of element regions and extending along a second axis; and a stop island disposed on the upper surface of the semiconductor film at an intersection between the first dicing street and the second dicing street, the stop island being in non-contact with the plurality of element regions. X_si>X_ds and Y_si<Y_ds are satisfied.

A silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.

A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.