An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.

An optoelectronic semiconductor chip has a non-rectangular, parallelogram-shaped top surface and an active zone, which is at a distance from the top surface and runs parallel to the top surface at least in places. The top surface includes a radiation exit surface, through which electromagnetic radiation generated during operation in the active zone emerges. The radiation exit surface has at least four vertices. The top surface includes at least one triangular connection area via which the active zone is electrically connectable.

A method for manufacturing a device (1) is suggested. The device comprises at least one opto-electronic module (1), and the method comprises creating a wafer stack (2) comprising a substrate wafer (PW), and an optics wafer (OW); wherein a multitude of active optical components (E) is mounted on the substrate wafer (PW), and the optics wafer (OW) comprises a multitude of passive optical components (L). Each of the opto-electronic modules (1) comprises at least one of the active optical components (E) and at least one of the passive optical components (L). The optics wafer (OW) can comprise at least one portion, referred to as blocking portion, which is at least substantially non-transparent for at least a specific wavelength range, and at least one other portion, referred to as transparent portion, which is at least substantially non-transparent for at least said specific wavelength range. 11. The opto-electronic module comprises a substrate member; an optics member; at least one active optical component mounted on said substrate member; and at least one passive optical component comprised in said optics member. The optics member (OW) is directly or indirectly fixed to said substrate member (PW). The opto-electronic modules (1) can have an excellent manufacturability while being small in dimension and having a high alignment accuracy.

The present disclosure is directed to LED components, and systems using such components, having a light emission profile that may be controlled independently of the lens shape by varying the position and/or orientation of LED chips with respect to one or both of an overlying lens and the surface of the component. For example, the optical centers of the LED emitting surface and the lens, which are normally aligned, may be offset from each other to generate a controlled and predictable emission profile. The LED chips may be positioned to provide a peak emission shifted from a perpendicular centerline of the lens base. The use of offset emitters allows for LED components with shifted or tilted emission patterns, without causing output at high angles of the components. This is beneficial as it allows a lighting system to have tilted emission from the LED component and primary optics.

A method for manufacturing a light distribution member has steps of providing a plurality of first light blocking film members, each of which including a first light blocking film covering a surface of a light-transmissive board, bonding a plurality of first light blocking film members, such that each first light blocking film is sandwiched between light-transmissive boards of adjacent first light blocking film members, to form a first bonded body, and cutting the first bonded body in a direction perpendicular to a lamination surface of the first light blocking film members so as to form a plurality of slices.

An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate, a scan line formed over the substrate and configured to provide a scan signal, and a data line crossing the scan line and configured to provide a data voltage. A driving voltage line crosses the scan line and is configured to provide a driving voltage. The display also includes a switching transistor electrically connected to the scan line and the data line and a driving transistor electrically connected to the switching transistor and including a driving gate electrode, a driving source electrode, and a driving drain electrode. The display further includes a storage capacitor including a first storage electrode formed over the driving transistor and the driving gate electrode as a second storage electrode. The second storage electrode overlaps the first storage electrode in the depth dimension and extends from the driving voltage line.

The present disclosure provides a lighting device comprising: a reflective element layer; an optical resin layer formed on the reflective element layer; a transparent electrode film layer formed on the optical resin layer; and a plurality of light-emitting units formed on the lower surface of the transparent electrode film layer. The lighting device allows the fundamental cause of the hot spot phenomenon to be eliminated, shows excellent luminous efficiency by efficiently performing the function of a surface light source, and enables the kinds of raw materials and the number of production processes to be reduced by eliminating the use of a PCB board and selectively applying second reflective patterns.

A display substrate and a manufacturing method and a display device are provided. The display substrate includes: a first electrode pattern, a connecting electrode pattern, a second electrode, and a light-emitting functional layer. The first electrode pattern is located in a display region and includes a plurality of first electrodes spaced apart from each other. The connecting electrode pattern is located in a peripheral region and includes a plurality of connecting electrodes. The second electrode is connected with the connecting electrode pattern, the second electrode and the first electrode pattern being spaced apart from each other. The light-emitting functional layer is located between the first electrode pattern and the second electrode, the connecting electrode pattern surrounds the first electrode pattern, and at least two of the plurality of connecting electrodes are each of a block shape and are spaced apart from each other.

Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.

A light emitting package is provided, the light emitting package includes a carrier having a main part that has multiple chip bonding regions, and each the chip bonding regions has two neighboring conductive parts. An insulating part is disposed on the main part and portion of the two neighboring conductive parts, and multiple hollow-out structures are formed by the insulating part and corresponded in position to the chip bonding regions. Each of the hollow-out structures has a side wall that surrounds the chip bonding regions, and the portion of the tops of the two neighboring conductive parts are exposed from a bottom portion of the hollow-out structure, and multiple light emitting chips are disposed onto the chip bonding surfaces.