H01L29/18

SEMICONDUCTOR DEVICE COMPRISING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

A semiconductor device including a two-dimensional material and a method of manufacturing the same are provided. The semiconductor device may include a first two-dimensional material layer including a first two-dimensional semiconductor material; a plurality of second two-dimensional material layers connected to the first two-dimensional material layer, each having a thickness greater than that of the first two-dimensional material layer, and including a doped two-dimensional semiconductor material; and a plurality of electrodes on the plurality of second two-dimensional material layers.

Liquid semiconductor-halogen based electronics

According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Liquid semiconductor-halogen based electronics

According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Quantum well stacks for quantum dot devices

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

Silicon carbide semiconductor device
11177348 · 2021-11-16 · ·

In a SiC-MOSFET, to increase the threshold voltage while reducing the channel resistance is difficult. And, when the channel resistance is lowered, the reliability may be reduced in such a manner that a current may flow when the device is turned off and malfunction may occur when the device is used as a normally-off device. According to the present invention, the threshold voltage is increased while the channel resistance is reduced, and reliability when used as a normally-off device is improved by adding at least any of sulfur, selenium, and tellurium to the channel region of the SiC MOSFET.

Silicon carbide semiconductor device
11177348 · 2021-11-16 · ·

In a SiC-MOSFET, to increase the threshold voltage while reducing the channel resistance is difficult. And, when the channel resistance is lowered, the reliability may be reduced in such a manner that a current may flow when the device is turned off and malfunction may occur when the device is used as a normally-off device. According to the present invention, the threshold voltage is increased while the channel resistance is reduced, and reliability when used as a normally-off device is improved by adding at least any of sulfur, selenium, and tellurium to the channel region of the SiC MOSFET.

Light emitting structure to aid LED light extraction

Display panels and methods of manufacture are described for down converting a peak emission wavelength of a pump LED within a subpixel with a quantum dot layer. In some embodiments, pump LEDs with a peak emission wavelength below 500 nm, such as between 340 nm and 420 nm are used. QD layers in accordance with embodiments can be integrated into a variety of display panel structures including a wavelength conversion cover arrangement, QD patch arrangement, or QD layers patterned on the display substrate.

Light-emitting device including light-emitting layer in which thermally activated delayed fluorescence bodies and quantum dots are dispersed and manufacturing apparatus of light-emitting device

To provide a light-emitting device that can obtain fluorescence having a narrow spectrum more efficiently, a light-emitting device includes: a light-emitting layer in which thermally activated delayed fluorescence bodies and quantum dots are dispersed; a first electrode in a lower layer than the light-emitting layer; and a second electrode in an upper layer than the light-emitting layer, wherein a light emission spectrum of the thermally activated delayed fluorescence bodies and an absorption spectrum of the quantum dots at least partially overlap each other.

Solid state light sheet having wide support substrate and narrow strips enclosing LED dies in series

A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING

Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.