Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, forming a gate spacer on opposing sides of the sacrificial gate structure, forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface having a first roughness, forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness, and subjecting the amorphized region to an annealing process to recrystallize the amorphized region to a crystalline region, and the crystalline region comprising a dislocation.

Provided is a semiconductor device in which a lifetime control region including a lifetime killer is provided, below a base region, from at least a part of a transistor portion to a diode portion, the transistor portion includes: a main region spaced apart from the diode portion in a top view; a boundary region located between the main region and the diode portion and overlapping the lifetime control region in a top view; and a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to a drift region through the base region, the plurality of gate trench portions include: a first gate trench portion provided in the main region; and a second gate trench portion provided in the boundary region, and a signal transmission timing of the first gate trench portion is different from a signal transmission timing of the second gate trench portion.

An integrated circuit (IC) device, and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure at a first lateral end of the multilayer stack; an epitaxial drain structure at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers between the gate structure and respective ones of the source structure and the drain structure, wherein at least one of the source structure or the drain structure does not exhibit a pattern of crystallographic defects extending from the inner spacers.

In an intermediate region surrounding a periphery of an active region, a gate polysilicon wiring layer is provided on a gate insulating film at a front surface of a semiconductor substrate, via a field oxide film. An inner end portion of the gate polysilicon wiring layer faces a p-type region of a surface region at the front surface of the semiconductor substrate, via only the gate insulating film. In the intermediate region, at corners thereof facing corners of the active region, a low carrier lifetime region containing a carrier lifetime killer is provided so as to overlap the p-regions and, in a depth direction, face the gate polysilicon wiring layer, whereby the lifetime of the minority carriers of the corner portions of the intermediate region is shorter than the lifetime of the minority carriers of linear portions of the intermediate region.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 μm or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 μm or more in a direction from the local maximum of the hydrogen peak toward the upper surface.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 μm or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 μm or more in a direction from the local maximum of the hydrogen peak toward the upper surface.

A semiconductor device including: a semiconductor substrate having a first and a second side, and including a donor layer with a doping concentration profile in a depth direction from the first to the second side. The donor layer includes: a first peak, situated at a first distance from the first side of said substrate; a first region adjacent to the first peak and extending in the depth direction from the first peak toward the first side, a second peak in said doping concentration profile, situated at a second distance from the first side of said substrate. Said second distance is less than said first distance and greater than zero; and a second region adjacent to the second peak and extending in the depth direction from the second peak toward the first side of the substrate, which has a doping concentration which is substantially uniform.

A semiconductor device including: a semiconductor substrate having a first and a second side, and including a donor layer with a doping concentration profile in a depth direction from the first to the second side. The donor layer includes: a first peak, situated at a first distance from the first side of said substrate; a first region adjacent to the first peak and extending in the depth direction from the first peak toward the first side, a second peak in said doping concentration profile, situated at a second distance from the first side of said substrate. Said second distance is less than said first distance and greater than zero; and a second region adjacent to the second peak and extending in the depth direction from the second peak toward the first side of the substrate, which has a doping concentration which is substantially uniform.

A semiconductor device is formed using a semiconductor substrate having a first main surface and a second main surface. A first semiconductor region of a first conductivity type is formed between the first main surface and the second main surface of the semiconductor substrate. A second semiconductor region is formed between the first semiconductor region and the first main surface. The first semiconductor region includes a hydrogen-related donor, and a concentration of the hydrogen-related donor of the first semiconductor region is equal to or larger than an impurity concentration of the first semiconductor region.