A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

A method of making a mobile ion regulated device includes stacking a dielectric layer on a substrate. Mobile ions are placed within the dielectric layer. An electrode layer is provided on the dielectric layer. The mobile ions are directed to a designated area of the dielectric layer.

The present invention relates to a method for manufacturing a nonvolatile memory thin film device by using a neutral particle beam generation apparatus. The present invention solves the problem that substrates such as glass and a plastic film may not be used for manufacturing the memory thin film device due to the high temperature heat treatment process for a long time, in the existing method for manufacturing the thin film device having the nonvolatile memory function by forming the mobile proton layer.

Resistive processing unit including: a plurality of transistors each having a lithium-doped region, wherein the plurality of transistors are arranged in an array to provide resistance; at least one first transmission line electrically connected to a source region of each transistor in at least one column of the array; at least one second transmission line electrically connected to a drain region of each transistor in at least one row of the array; and at least one third transmission line electrically connected to a gate region of the plurality of transistors in at least one row of the array; wherein application of an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line mobilizes lithium ions in the lithium region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride. The second layer includes nickel oxide, tin oxide, copper oxide, nickel oxynitride, tin oxynitride, or copper oxynitride. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate and on two opposite sides of the gate stack.

A semiconductor package and a manufacturing method thereof are provided. The package includes a substrate, and first, second and third semiconductor elements disposed on and electrically connected to the substrate. A heat transfer enhancing layer, a thermal conductive material layer and an adhesive material layer are respectively disposed on and joined to the first, second and third semiconductor elements. A lid is disposed over the first, second and third semiconductor elements, and joined to the heat transfer enhancing layer, the thermal conductive material layer and the adhesive material layer. The thermal conductive material layer has a thermal conductivity lower than that of the heat transfer enhancing layer and higher than that of the adhesive material layer, and the thermal conductive material layer has a bonding strength larger than that of the heat transfer enhancing layer and smaller than that of the adhesive material layer.

A FET with a multi-value switching function comprises a source region, a channel region, a drain region, a gate dielectric layer, a substrate layer, a gate-oxide inducer layer, a metal layer and a spacer layer. The channel region is an undoped channel region, the drain region is an undoped drain region. The metal layer comprises first to third metal blocks which are arranged at intervals from left to right, the distance between the first metal block and the second metal block is 12 nm, the distance between the second metal block and the third metal block is 10 nm, the first metal block is a main control gate of the FET, the second metal block and the third metal block are two inducer gates of the FET, and the spacer layer is used for isolating the first metal block from the second metal block and the third metal block.

A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.

According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.