Embodiments provide a transistor structure, a semiconductor structure and a fabrication method thereof. The method for fabricating a transistor structure includes: providing a substrate; forming a channel layer on an upper surface of the substrate, the channel layer including a two-dimensional layered transition metal material layer; forming a source and a drain on two opposite sides of the channel layer, respectively; forming a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source, and the drain; and forming a gate on an upper surface of the gate dielectric layer, the gate being positioned at least directly above the channel layer.

A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.

An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.

A semiconductor device according to an embodiment includes a plurality of conductive layers stacked apart from each other and extending in a plate shape in a direction crossing a stacking direction; a channel body including a semiconductor film and penetrating the plurality of conductive layers; a memory film including a charge accumulation film and provided between the plurality of conductive layers and the channel body; and a high dielectric constant (high-k) film arranged between the plurality of conductive layers and the memory film while being divided in a circumferential direction surrounding the memory film.

A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.

Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

A NAND structure and method of fabricating the structure are described. A multi-layer ONON stack is deposited on a Si substrate and a field oxide grown thereon. A portion of the field oxide is removed, and high-aspect-ratio channels are etched in the stack. The channels are filled with a Si oxide using a thermal ALD process. The thermal ALD process includes multiple growth cycles followed by a passivation cycle. Each growth cycle includes treating the surface oxide surface using an inhibitor followed by multiple cycles to deposit the oxide on the treated surface using a precursor and source of the oxide. The passivation after the growth cycle removes the residual inhibitor. The Si oxide is recess etched using a wet chemical etch of DHF and then capped using a poly-Si cap.

Thin film transistors having edge-modulated two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a device layer including a two-dimensional (2D) material layer above a substrate, the 2D material layer including a center portion and first and second edge portions, the center portion consisting essentially of molybdenum or tungsten and of sulfur or selenium, and the first and second edge portions including molybdenum or tungsten and including tellurium.