The present disclosure provides a method of manufacturing a semiconductor device. Furthermore the present disclosure provides a photovoltaic device and a light emitting diode manufactured in accordance with the method. The method comprises the steps of forming a germanium layer using deposition techniques compatible with high-volume, low-cost manufacturing, such as magnetron sputtering, and exposing the germanium layer to laser light to reduce the amount of defects in the germanium layer. After the method is performed the germanium layer can be used as a virtual germanium substrate for the growth of III-V materials.

In an embodiment a method includes providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region, directly applying a nucleation layer of oxygen-containing AlN to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.

A solar cell contact arrangement, having a semiconductor body with a top and a bottom, wherein the semiconductor body has multiple solar cell stacks and includes a support substrate on the bottom, and each solar cell stack has at least two III-V subcells arranged on the support substrate and at least one through-contact extending from the top to the bottom of the semiconductor body with a continuous side wall, wherein the through-contact has a first edge region on the top and a second edge region on the bottom, and the first edge region has a first section and a second, metallic section, and the second edge region has a first section and a second section, wherein the respective second sections completely enclose the respective first sections, and an insulating layer.

A multijunction solar cell assembly and its method of manufacture including interconnected first and second discrete semiconductor body subassemblies disposed adjacent and parallel to each other, each semiconductor body subassembly including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected subassemblies form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor body and the bottom solar subcell in the second semiconductor body.

A Group III nitride semiconductor containing: a RAMO.sub.4 substrate containing a single crystal represented by the general formula RAMO.sub.4 (wherein R represents one or a plurality of trivalent elements selected from the group consisting of Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from the group consisting of Fe (III), Ga, and Al, and M represents one or a plurality of divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), and a Group III nitride crystal disposed above the RAMO.sub.4 substrate, having therebetween a dissimilar film that contains a material different from the RAMO.sub.4 substrate, and has plural openings.

A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.

A method of growing a III-V semiconductor compound film for a semiconductor device including the steps of depositing a textured oxide buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, the metal being a component of a III-V compound and forming a layer on the inorganic film on which additional elements from the III-V compound are added, forming a top layer of a tandem solar cell.

An optical transducer system that has a light source and a transducer. The light source generates light that has a predetermined photon energy. The transducer has a bandgap energy that is smaller than the photon energy. An increased optical to electrical conversion efficiency is obtained by illuminating the transducer at increased optical power densities. A method of converting optical energy to electrical energy is also provided.

A device, system, and method for a multi junction solar cell are described herein. An exemplary multi-solar cell structure can have a substrate having a first surface having a (111) crystalline etched surface. A dielectric layer can be deposited on the first surface of the substrate. A graded buffer layer can be grown on a second surface of the substrate with the second surface having a (100) crystalline surface. A first solar subcell within or on top of the graded buffer layer and a second solar subcell grown on top of the first solar subcell.

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×10.sup.16 cm.sup.−3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.