There are disclosed herein various implementations of a semiconductor component with a multi-layered nucleation body and method for its fabrication. The semiconductor component includes a substrate, a nucleation body situated over the substrate, and a group III-V semiconductor device situated over the nucleation body. The nucleation body includes a bottom layer formed at a low growth temperature, and a top layer formed at a high growth temperature. The nucleation body also includes an intermediate layer that is formed substantially continuously using a varying intermediate growth temperature.

A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

Thin freestanding nitride veneers can be used for the fabrication of semiconductor devices. These veneers are typically less than 100 microns thick. The use of thin veneers also eliminates the need for subsequent wafer thinning for improved thermal performance and 3D packaging.

A stack-like III-V semiconductor product comprising a substrate and a sacrificial layer region arranged on an upper side of the substrate and a semiconductor layer arranged on an upper side of the sacrificial layer region. The substrate, the sacrificial layer region and the semiconductor layer region each comprise at least one chemical element from the main groups III and a chemical element from the main group V. The sacrificial layer region differs from the substrate and from the semiconductor layer in at least one element. An etching rate of the sacrificial layer region differs from an etching rate of the substrate and from an etching rate of the semiconductor layer region at least by a factor of ten. The sacrificial layer region is adapted in respect of its lattice to the substrate and to the semiconductor layer region.

A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h-.sup.10BN or h-BN or .sup.10BN or BN) having a thickness (t), dicing or cutting the epilayer wafer into one or more BN strips having a width (W) and a length (L), and depositing a first metal contact on a first surface of at least one of the BN strip and a second metal contact on a second surface of the at least one BN strip. The neutron detector includes an electrically insulating submount, a BN epilayer of Boron-10 enriched hexagonal boron nitride (h-.sup.10BN or h-BN or .sup.10BN or BN) placed on the insulating submount, a first metal contact deposited on a first surface of the BN epilayer, and a second metal contact deposited on a second surface of the BN epilayer.

Techniques are disclosed for fabricating and using a neuromorphic computing device including biological neurons. For example, a method for fabricating a neuromorphic computing device includes forming a channel in a first substrate and forming at least one sensor in a second substrate. At least a portion of the channel in the first substrate is seeded with a biological neuron growth material. The second substrate is attached to the first substrate such that the at least one sensor is proximate to the biological neuron growth material and growth of the seeded biological neuron growth material is stimulated to grow a neuron in the at least a portion of the channel.

Techniques for processing materials for manufacture of gallium-containing nitride substrates are disclosed. More specifically, techniques for fabricating and reusing large area substrates using a combination of processing techniques are disclosed. The methods can be applied to fabricating substrates of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others. Such substrates can be used for a variety of applications including optoelectronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photo detectors, integrated circuits, transistors, and others.

The present invention relates to a betavoltaic battery comprising: a substrate; an intrinsic semiconductor unit disposed on the substrate; an N-type semiconductor unit and a P-type semiconductor unit that are disposed on at least a portion of a surface of the intrinsic semiconductor unit and arranged alternately; and beta ray sources that are disposed on the N-type semiconductor unit and the P-type semiconductor unit. The present invention also relates to a method for manufacturing a betavoltaic battery, comprising the steps of: (A) forming an intrinsic semiconductor unit on a substrate; (B) forming an N-type semiconductor unit and a P-type semiconductor unit alternately by irradiating at least a portion of the surface of the intrinsic semiconductor unit with an ion beam; and (C) disposing a beta ray source on the N-type semiconductor unit and the P-type semiconductor unit.

A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.

A method of manufacturing a solar cell that includes providing a semiconductor growth substrate; depositing on said growth substrate a sequence of layers of semiconductor material forming a solar cell; applying a metal contact layer over said sequence of layers; affixing the adhesive polyimide surface of a permanent supporting substrate directly over said metal contact layer and permanently bonding it thereto by a thermocompressive technique; and removing the semiconductor growth substrate.