An optoelectronic integrated substrate, a preparation method thereof and an optoelectronic integrated circuit. The electronic integrated substrate includes a base substrate and an electronic device and a photo-diode disposed on the base substrate, wherein the photo-diode includes an ohmic contact layer and an intrinsic amorphous silicon layer, and the ohmic contact layer and the intrinsic amorphous silicon layer are sequentially arranged along a direction parallel to the plane of the base substrate and are connected.

Disclosed in embodiments of the present disclosure are a display panel and a manufacturing method therefor, and a display apparatus. The display panel includes: a base substrate; an organic functional film layer provided on the base substrate; an insulating layer provided on the organic functional film layer, a plurality of dents distributed at intervals are provided on one side of the insulating layer distant from the organic functional film layer; and an amorphous silicon solar cell film layer provided at one side of the insulating layer distant from the organic functional film layer, the amorphous silicon solar cell film layer has the same morphology as the surface of the insulating layer where the dents are provided.

A photosensitive sensor, a manufacturing method thereof and a display panel are provided. The photosensitive sensor includes a first type semiconductor layer, an intrinsic semiconductor layer disposed on a side of the first type semiconductor layer, and a second type semiconductor layer disposed on a side of the intrinsic semiconductor layer away from the first type semiconductor layer. The intrinsic semiconductor layer is provided with metal particles capable of generating a surface plasmon effect. The metal particles are dispersely distributed in the intrinsic semiconductor layer.

Disclosed is an interdigitated back contact photovoltaic device that includes a first patterned silicon layer situated on an intrinsic layer, and having the same type of doping as the one of the substrate. First charge collection portions are deposited on predetermined areas of the intrinsic layer, and include each an amorphous layer portion situated between the predetermined areas and the at least partially nano-crystalline layer portions. The amorphous layer portions have a larger width than the width of the nano-crystalline layer portions. On top if the first patterned silicon layer, a second nano-crystalline silicon layer is deposited that has a doping of a second type being the other of the p-type doping or the n-type doping with respect to the doping-type of the first patterned silicon layer.

A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

The production process according to the invention consists of a nanometric scale transformation of the crystalline silicon in a hybrid arrangement buried within the crystal lattice of a silicon wafer, to improve the efficiency of the conversion of light into electricity, by means of hot electrons. All the parameters, procedures and steps involved in manufacturing giant photoconversion cells have been tested and validated separately, by producing twenty series of test devices. An example of the technology consists of manufacturing a conventional crystalline silicon photovoltaic cell with a single collection junction and completing the device thus obtained by an amorphizing ion implantation followed by a post-implantation thermal treatment. The modulation of the crystal, specific to the giant photoconversion, is then carried out on a nanometric scale in a controlled manner to obtain SEGTONs and SEG-MATTER which are active both optically and electronically, together with the primary conversion of the host converter.

Provided are a solar cell having a good conversion efficiency in which damage to a p-n junction structure is prevented when an antireflection film is removed, and a method of manufacturing such a solar cell.

Disclosed is an interdigitated back contact photovoltaic device that includes a first patterned silicon layer situated on an intrinsic layer, and having the same type of doping as the one of the substrate. First charge collection portions are deposited on predetermined areas of the intrinsic layer, and include each an amorphous layer portion situated between the predetermined areas and the at least partially nano-crystalline layer portions. The amorphous layer portions have a larger width than the width of the nano-crystalline layer portions. On top if the first patterned silicon layer, a second nano-crystalline silicon layer is deposited that has a doping of a second type being the other of the p-type doping or the n-type doping with respect to the doping-type of the first patterned silicon layer.

A flat panel detector includes a base substrate, a sensing electrode and a bias electrode over the base substrate, and an insulating layer over the sensing electrode and the bias electrode at a side distal from the substrate. A difference between thicknesses of regions of the insulating layer corresponding to the sensing electrode and the bias electrode respectively is not greater than a preset threshold. When a sufficiently high voltage is applied to the insulating layer and turned on, because the thickness thereof is relatively uniform, a dark current generated by the sensing electrode and the bias electrode under the insulating layer is relatively uniform, thereby improving detection accuracy of the flat panel detector.