Patent classifications
H01L2224/0212
Semiconductor device
A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.
3D chip-on-wafer-on-substrate structure with via last process
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
Chip-on-wafer package and method of forming same
A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.
METHOD FOR IMPROVING WIRE BONDING STRENGTH OF AN IMAGE SENSOR
A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.
3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
3D chip-on-wafer-on-substrate structure with via last process
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.
MEMS having a cutout section on a concave portion between a substrate and a stationary member
A functional element includes a substrate which is provided with a concave section; a stationary section connected to a wall section that defines the concave section of the substrate; an elastic section which extends from the stationary section and is capable of stretching and contracting in a first axis direction; a movable body connected to the elastic section; a movable electrode section which extends from the movable body. The concave section includes a cutout section which is provided on the wall section. The stationary section includes an overlap section which is spaced with the substrate, and overlaps the concave section when seen in a plan view. At least a portion of the overlap section overlaps the cutout section when seen in the plan view, and the elastic section extends from the overlap section.
Device for controlling trapped ions
A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.
Semiconductor devices with flexible spacer including a support structure and methods of making the same
A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.