A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

A memory device including at least one dummy word line over a substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line. The method including performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.

A memory device including at least one dummy word line over a substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line. The method including performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.