A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

A stacked die structure includes a base die, a top die and conductive terminals electrically connected to the top die. The base die includes a base semiconductor substrate, a base interconnection layer disposed on the base semiconductor substrate, and a base bonding layer disposed on the base interconnection layer. The top die is stacked on the base die and electrically connected to the base die, wherein the top die includes a top bonding layer, a top semiconductor substrate, a top interconnection layer, top conductive pads and top grounding vias. The top bonding layer is hybrid bonded to the base bonding layer. The top interconnection layer is disposed on the top semiconductor substrate and includes a dielectric layer, conductive layers embedded in the dielectric layer, and conductive vias joining the conductive layers. The conductive pads and top grounding vias are embedded in the dielectric layer and disposed on the conductive layers.

A stacked die structure includes a base die, a top die and conductive terminals electrically connected to the top die. The base die includes a base semiconductor substrate, a base interconnection layer disposed on the base semiconductor substrate, and a base bonding layer disposed on the base interconnection layer. The top die is stacked on the base die and electrically connected to the base die, wherein the top die includes a top bonding layer, a top semiconductor substrate, a top interconnection layer, top conductive pads and top grounding vias. The top bonding layer is hybrid bonded to the base bonding layer. The top interconnection layer is disposed on the top semiconductor substrate and includes a dielectric layer, conductive layers embedded in the dielectric layer, and conductive vias joining the conductive layers. The conductive pads and top grounding vias are embedded in the dielectric layer and disposed on the conductive layers.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for electrical connection to an internal circuit of the semiconductor device. The subsidiary portion is provided for probing, in particular, for testing high frequency performance of the semiconductor device by probing with a RF-probe. Because the subsidiary portion is independent from the primary portion, the subsidiary portion does not affect the electrical performance of the semiconductor device. Also, the subsidiary portion has a narrowed contact area with respect to the RF-probe to lessen adherence of metal flakes from the pad onto the probe.

A semiconductor device having a composite pad including a primary portion and a subsidiary portion is disclosed. The primary portion is provided for electrical connection to an internal circuit of the semiconductor device. The subsidiary portion is provided for probing, in particular, for testing high frequency performance of the semiconductor device by probing with a RF-probe. Because the subsidiary portion is independent from the primary portion, the subsidiary portion does not affect the electrical performance of the semiconductor device. Also, the subsidiary portion has a narrowed contact area with respect to the RF-probe to lessen adherence of metal flakes from the pad onto the probe.

Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.