Flip chip alignment mark exposing method enabling wafer level underfill

Abstract

Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Claims

1. A method comprising: selecting a portion of a substantially optically opaque coating to be removed from an attachment surface of a semiconductor device that carries a plurality of solder bumps and at least one feature between two of the plurality of solder bumps, the plurality of solder bumps and the at least one feature being obscured by the substantially optically opaque coating, the obscuring of the at least one feature hindering processing of the semiconductor device; removing the selected portion of the coating using laser ablation, thereby exposing a portion of the semiconductor device attachment surface including the at least one feature; and cleaning the exposed portion of the semiconductor device and a surrounding surface of the coating.

2. The method of claim 1, wherein the at least one feature between two of the plurality of solder bumps includes an alignment mark, and the selecting a portion includes selecting a region of the surface of the semiconductor device that includes the alignment mark.

3. The method of claim 1, wherein the coating includes a B-staged resin doped with a thermally enhancing filler, the doped resin being substantially optically opaque in a cured state.

4. The method of claim 3, wherein the filler includes fused silica.

5. The method of claim 1, wherein the removing the selected portion using laser ablation includes exposing the selected portion to ultraviolet laser radiation.

6. The method of claim 5, wherein the ultraviolet laser radiation has a wavelength of from about 100 nm to about 400 nm.

7. The method of claim 5, wherein the laser radiation has a fluence of from about 200 mJ/cm.sup.2 to about 2000 mJ/cm.sup.2.

8. The method of claim 5, wherein the laser radiation is pulsed at a frequency of from about 100 Hz to about 800 Hz.

9. The method of claim 1, wherein the removing of the selected portion and the cleaning of the exposed semiconductor device surface and surrounding coating surface are performed before dicing of the semiconductor device.

10. The method of claim 1, wherein the removing of the selected portion and the cleaning of the exposed semiconductor device surface and a surrounding coating surface are performed after dicing of the semiconductor device.

11. A preparation method for a semiconductor device having an attachment surface that carries a plurality of solder bumps and at least one attachment alignment mark between two of the plurality of solder bumps, the attachment surface being coated with a substantially optically opaque coating material that obscures the at least one attachment alignment mark, the preparation method comprising: selecting a portion of the coating material overlying an attachment alignment mark located between two of the plurality of solder bumps; removing the selected portion of the coating material using laser ablation, thereby exposing the respective alignment mark and a respective portion of the attachment surface, including a portion of the attachment surface between the two of the plurality of solder bumps; and cleaning the respective portion of the attachment surface and a surrounding surface of the coating material.

12. The method of claim 11, further comprising B-staging the coating material before removing the selected portion.

13. The method of claim 11, further comprising dicing the semiconductor device into singulated chips before the removing of the selected portion.

14. The method of claim 11, further comprising dicing the semiconductor device into singulated chips after the cleaning of the exposed attachment surface.

15. The method of claim 11, wherein the removing of the selected portion using laser ablation includes directing ultraviolet laser radiation at the selected portion.

16. The method of claim 15, wherein the ultraviolet laser radiation has a wavelength of from about 100 nm to about 400 nm.

17. The method of claim 11, wherein the removing of the selected portion using laser ablation includes producing laser radiation with an excimer laser in pulses at a rate of from about 100 Hz to about 500 Hz and a fluence of from about 200 mJ/cm.sup.2 to about 1000 mJ/cm.sup.2.

18. A method comprising: applying a wafer level underfill (WLUF) coating to an attachment surface of a semiconductor device article, the attachment surface including a plurality of solder bumps and a plurality of alignment marks, the coating having a thickness extending beyond an end of a furthest projecting solder bump, thereby obscuring the plurality of alignment marks, including at least one alignment mark located between two of the plurality of solder bumps; selecting portions of the WLUF coating corresponding to the obscured plurality of alignment marks including the at least one alignment mark located between the two of the plurality of solder bumps; ablating the selected portions of the WLUF coating with a laser ablation system, thereby exposing the obscured plurality of alignment marks including the at least one alignment mark located between the two of the plurality of solder bumps; and cleaning the exposed alignment marks and surrounding portions of the attachment surface and the WLUF coating.

19. The method of claim 18, wherein the laser ablation system directs ultraviolet radiation at the selected portions.

20. The method of claim 19, wherein the laser ablation system employs an excimer laser producing ultraviolet radiation pulses at a frequency of from about 100 Hz to about 500 Hz at a fluence of from about 200 mJ/cm.sup.2 to about 1000 mJ/cm.sup.2 at a wavelength of from about 100 nm to about 400 nm.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings.

(2) FIG. 1 is a schematic side view illustration of a typical prior art die that can be prepared according to embodiments of the invention disclosed herein.

(3) FIG. 2 is a schematic top view illustration of the typical prior art die shown in FIG. 1 according to embodiments of the invention disclosed herein.

(4) FIG. 3 is a schematic side view illustration of a die with a coating applied according to embodiments of the invention disclosed herein.

(5) FIG. 4 is a schematic top view illustration of the die shown in FIG. 3 with a coating applied according to embodiments of the invention disclosed herein.

(6) FIG. 5 is a schematic side view illustration of a selected portion of a coating on a die being removed according to embodiments of the invention disclosed herein.

(7) FIG. 6 is a schematic side view illustration of exposed surfaces and/or regions surrounding a removal area being cleaned according to embodiments of the invention disclosed herein.

(8) FIG. 7 is a schematic top view illustration of a coated die with a portion of the coating removed according to an embodiment of the invention disclosed herein.

(9) FIG. 8 is a schematic illustration of dicing a die in accordance with aspects of embodiments of the invention disclosed herein.

(10) FIGS. 9 and 10 are schematic illustrations of preparing a singulated chip for attachment to a substrate according to embodiments of the invention disclosed herein.

(11) FIGS. 11-15 schematically illustrate an attachment process used with dies to which embodiments of the invention disclosed herein have been applied.

DETAILED DESCRIPTION

(12) Embodiments of the present invention are directed to a technique that can be used to enable wafer level underfill (WLUF) coating use in semiconductor device fabrication, particularly for finer photolithography processes producing smaller scale elements, such as, for example, in multiple patterning lithography technology, though the advantages of embodiments can be enjoyed in more conventional current fabrication processes, as well. While embodiments may be described with respect to attachment using solder bumps in flip-chip techniques, embodiments may additionally be used with other attachment techniques. Likewise, while embodiments are described primarily with reference to WLUF coatings, embodiments can be employed with other attachment mark obscuring coatings and/or processes. As is known, a die including multiple chips is typically diced prior to attachment. Embodiments of the invention disclosed herein can be applied before or after dicing as may be suitable, desirable, and/or appropriate. Further, embodiments can be used in conjunction with known WLUF techniques, such as that disclosed in U.S. Patent Application Publication No. 2009/0108472 to Feger et al., the disclosure of which is incorporated by reference.

(13) Returning to FIGS. 1 and 2, a die 10 including a device layer 12, an attachment layer 14, connection pads 16, and solder bumps 18 can be fabricated by known techniques, such as C4 fabrication processes. In addition, alignment marks 20 can be applied to an attachment surface 15 of die 10, which can also be formed and/or applied using known techniques. As noted above, it should be understood that attachment layer 14 can typically include a passivation layer, but could instead be some other type of material layer, or that additional layers can be applied over device layer 12 and/or attachment layer 14 within the scope of embodiments. For example, attachment layer 14 can include an electrically conductive protective layer using techniques disclosed in U.S. Pat. No. 8,994,173 to Daubenspeck et al., the disclosure of which is incorporated by reference. Still further, die 10 can be formed by any number of known processes and materials used in semiconductor device fabrication, all of which are well known in the art and to those of ordinary skill therein. The specific processes and materials used to form die 10 are not necessarily of import to embodiments of the invention disclosed herein beyond knowledge of material properties of device layer 12, attachment layer 14, pads 16, and solder bumps 18, so that appropriate WLUF coating material and/or filler can be selected. For example, a typical passivation layer can include polyimide in various incarnations, some photoresponsive and some non-photoresponsive, all of whose properties are well known in the art. In addition, solder bump composition and properties thereof are well known, as are the compositions and properties of a wide variety of other materials that can be used in attachment layer 14. Further, embodiments can be incorporated into existing fabrication processes as steps between completion of bump formation and chip attachment, before and/or after dicing of the die into individual chips.

(14) With reference to FIGS. 3 and 4, embodiments include applying a coating 30 over attachment surface 15 and solder bumps 18, covering alignment marks 20 and presenting a coating surface 32 used in attachment, as will be described. Coating 30 can include a wafer level underfill (WLUF) coating, such as a resin, though other materials can be used. For example, a B-staged resin could be employed, which could be a thermally setting resin. If needed, suitable, and/or desirable, WLUF coating 30 can include a filler or other modifying material to alter its thermal and/or chemical properties. For example, WLUF coating 30 can include a silica filler to reduce a coefficient of thermal expansion (CTE) of the WLUF coating to reduce stresses induced during attachment as well be described. Where a thermally setting resin is used, die 10 can be placed in an environment in which temperature can be controlled, such as to maintain temperature of the WLUF coating at a cure temperature for a required cure period.

(15) Depending on the particular WLUF coating material and/or filler(s) employed, alignment marks 20 may be partially or completely obscured from view by machinery used in flip chip attachment processes. To allow use of WLUF materials with such optical properties, such as partially or substantially optically opaque materials, embodiments provide a way to expose one or more of alignment marks 20 to allow such machinery to detect marks 20. Broadly, a portion of WLUF coating 30 can be selected for removal, the selected portion can be removed, and any exposed surface(s) and/or surrounding surface(s) can be cleaned. While it is possible the removal could be performed such that soot or other materials does not form on exposed and/or surrounding surface(s), cleaning should still be performed since very slight changes in conditions during removal could result in unexpected deposition of such materials, which could adversely affect attachment, electrical connections, and/or mechanical connections of the final chip(s) and/or semiconductor device(s). Again, while the example described shows selection, removal, and cleaning occurring before dicing, it should be readily apparent that these steps can be performed on singulated chips 60 (FIGS. 8-10) after dicing if so desired and/or appropriate.

(16) Turning now to FIG. 5, a portion of WLUF coating 30 can be selected for removal, and the selected portion can be removed. In the example shown in FIG. 5, a laser ablation system 40 can be used to remove the selected portion of WLUF coating 30. Such a laser ablation system 40 can include a laser 42 that can produce radiation 44 targeted at the selected portion of WLUF coating 30. For example, laser 42 can take the form of an excimer laser producing ultraviolet radiation in pulses of a particular fluence to ablate WLUF coating material with a low transfer of heat to surrounding materials. In embodiments, another type of laser could be employed and/or other wavelengths of radiation, fluences, pulse duration/frequency, and/or other aspects of laser ablation can be varied. For example, a gas discharge laser, semiconductor laser, or other type of laser could be used, or a maser or other type of device producing coherent radiation could be used so long as the selected portion of WLUF coating 30 can be ablated with relatively little heat transfer to surrounding material(s) of die 10. In the particular example shown, a laser producing coherent radiation at a wavelength of from about 100 nm to about 400 nm at a fluence of from about 200 mJ/cm.sup.2 to about 2000 mJ/cm.sup.2 when in pulses at a frequency of from about 100 Hz to about 800 Hz. For many B-stage resins with silica filler(s), radiation at a wavelength of from about 250 nm to about 350 nm at a fluence of from about 200 mJ/cm.sup.2 to about 1000 mJ/cm.sup.2 when in pulses at a frequency of from about 100 Hz to about 500 Hz can be employed. As used herein, “about” indicates +/−10% change in the value stated. In one embodiment, satisfactory efficacy was observed using a wavelength of about 308 nm at a fluence of about 500 mJ/cm2 in about 500 pulses at a pulse frequency of about 200 Hz.

(17) Continuing now to FIG. 6, a cleaning station 50 can be used to clean any exposed surface(s) and/or surrounding area(s) after removal of the selected portion of WLUF coating 30. For example, a water jet system can include a nozzle or the like 52 that can direct a water jet 54 at exposed surface(s) and/or surrounding area(s) after removal. It should be apparent, however, that any suitable cleaning station and/or system could be employed, and using a cleaning station and/or system already present and used in a semiconductor fabrication process presents cost and efficiency improvement opportunities.

(18) As illustrated in FIG. 7, a groove or the like 34 can be formed by the removal process, exposing one or more alignment marks 20 on attachment surface 15, possibly also exposing one or more of solder bumps 18, depending on the particular orientation and/or path of removal, as well as the shape and/or location of the portion of WLUF coating 30 selected for removal.

(19) Fabrication can continue by dicing die 10 into singulated chips 60, as shown in FIG. 8, which can be attached to a bonder head 62 (FIG. 9) as shown in FIGS. 9 and 10, yielding an attachment article 64. As shown in FIG. 11, attachment article 64 can then be presented with coating surface 32 (FIG. 5) facing an attachment assembly 70 including a base plate 72 supporting a substrate 74, at which point force can be applied to attachment article 64 and/or attachment assembly 70 to bias WLUF coating 30 (FIG. 5) toward substrate 74. Substrate 74 can include pads 76 to which solder bumps 18 (FIG. 5) can be joined, pads 76 corresponding in number and location to solder bumps 18 of chips 60. Substrate 74 can also include additional bumps 78 formed on pads 76 to further enhance connection if so desired and/or appropriate, such as pre-solder bumps for chip-to-laminate-substrate bonding. In addition to force, temperature can be controlled, such as by elevating temperature of WLUF coating 30 to a flow temperature. By continuing to bias article 64 toward assembly 70, solder bumps 18 can be forced through WLUF coating 30 and/or WLUF coating 30 can flow over a surface of substrate 74 to allow solder bumps 18 to move into contact with pads 76, as illustrated in FIGS. 12 and 13. Temperature can further be controlled to cause solder bumps 18 to flow until as much electrical and/or mechanical contact has been achieved therebetween as may be suitable and/or desired, as illustrated in FIG. 14. Typically, this second temperature is higher than the temperature used to flow and/or remove WLUF coating 30, and a cure temperature of WLUF coating 30 can be at the first temperature or between the first and second temperatures. To avoid curing of WLUF coating 30, temperature can be increased or ramped over a relatively short time. Once suitable and/or desired electrical and/or mechanical connection has been achieved, chip 60 and substrate 74 form a packaged device 80 from which bonder head 62 can be removed, as shown in FIG. 15. Packaged device 80 can then be processed as needed prior to shipment.

(20) In embodiments, force and/or temperature used can vary depending on a variety of factors, including die size, the particular material(s) used to form solder bumps 18, WLUF coating 30, and/or pads 76, as well as, where appropriate, bumps 78. For example, for a chip-to-chip bonding arrangement of a device on the order of 650 mm.sup.2 where solder bumps 18 include a tin-silver (SnAg) solder, corresponding pads 76 include a nickel and gold (Ni/Au) material, the bonding head can be heated to about 150° C., the stage can be heated to about 150° C., and about 450N of force can be applied for about 5 s in a first step to flow and/or remove the WLUF coating, and the head can be heated to 375° C., the stage can be maintained at 150° C., and force can be maintained at 450N for about 15 s in a second step to flow the solder bumps/joining As suggested above, heating to the second temperature can be done at a rate to avoid curing of WLUF coating 30, such as, for example, at a rate of about 50° C./second for the materials and temperatures used in this example, though the rate can differ for other materials and/or combinations of materials and/or other conditions. It should be noted that larger die size (area) can result in greater applied force, and smaller die size (area) can result in lesser applied force. It should also be noted that applied force can vary between steps so that a force of one magnitude can be applied during WLUF coating flow/removal, and a force of another magnitude can be applied during solder flow, again depending on factors such as, but not limited to, die size and materials used and/or properties thereof.

(21) By including WLUF coating 30, solder bumps 18 and attachment surface 15 can be protected from damage and/or chemical reactions that might occur prior to attachment. In addition, WLUF coating 30 can reduce thermal and mechanical stresses induced on chips 60 during attachment, increasing effective fabrication yield and overall quality of product. Further, employing embodiments to enable use of WLUG coating 30 can eliminate flux residue cleaning, baking, and/or plasma capillary underfill flow time.

(22) The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.