One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

Embodiments disclosed herein include die modules. In an embodiment, a die module comprises a plurality of first dies, and a second die under the plurality of first dies. In an embodiment, the second die is coupled to individual ones of the plurality of first dies. In an embodiment, the second die comprises a plurality of mesh stops, and conductive routing to electrically couple the mesh stops together.

Embodiments disclosed herein include die modules. In an embodiment, a die module comprises a plurality of first dies, and a second die under the plurality of first dies. In an embodiment, the second die is coupled to individual ones of the plurality of first dies. In an embodiment, the second die comprises a plurality of mesh stops, and conductive routing to electrically couple the mesh stops together.

An integrated circuit includes a first die and a second die. The second die is embedded or otherwise contained in a layered interconnect structure of the first die. The second die can be an IC die or it can be an electrically inactive element, such as a heat spreader. A portion of the layered interconnect structure is laterally adjacent to the second die. A first part of the second die can be electrically connected to a second part of the second die via the interconnect structure of the first die. The second die can be operatively coupled to the first die using electrical connections between the second die and one or more interconnect layers above or below the second die, or to devices of the first die. A method of fabricating an interconnect structure with one or more embedded dies is also disclosed.

An integrated circuit includes a first die and a second die. The second die is embedded or otherwise contained in a layered interconnect structure of the first die. The second die can be an IC die or it can be an electrically inactive element, such as a heat spreader. A portion of the layered interconnect structure is laterally adjacent to the second die. A first part of the second die can be electrically connected to a second part of the second die via the interconnect structure of the first die. The second die can be operatively coupled to the first die using electrical connections between the second die and one or more interconnect layers above or below the second die, or to devices of the first die. A method of fabricating an interconnect structure with one or more embedded dies is also disclosed.

A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.