H01L2224/27

Wound body of sheet for sintering bonding with base material
11697567 · 2023-07-11 · ·

To provide a wound body of a sheet for sintering bonding with a base material that realizes a satisfactory operational efficiency in a process of producing a semiconductor device comprising sintering bonding portions of semiconductor chips and that also has both a satisfactory storage stability and a high storage efficiency. A wound body 1 according to the present invention has a form in which a sheet for sintering bonding with a base material X is wound around a winding core 2 into a roll shape, the sheet for sintering bonding with a base material X having a laminated structure comprising: a base material 11; and a sheet for sintering bonding 10, comprising an electrically conductive metal containing sinterable particle and a binder component.

METHOD FOR THE LOCALIZED DEPOSITION OF A MATERIAL ON A METAL ELEMENT

A method is provided for localised deposition of a material over an element, including deposition of a portion of the material over a portion of a surface of a support; positioning of a portion of the element against the portion of the material; annealing of the material portion increasing, at the end of the treatment, the adhesion force of the material against the portion of the element, the materials of the portion of the element and of the portion of the surface of the support being selected such that the adhesion of the material against the portion of the element is, at the end of the annealing, higher than that of the material against the portion of the surface of the support; and separation of the element and the support at the interface between the material and the portion of the surface of the support, the material remaining secured to the portion of the element.

METHOD FOR THE LOCALIZED DEPOSITION OF A MATERIAL ON A METAL ELEMENT

A method is provided for localised deposition of a material over an element, including deposition of a portion of the material over a portion of a surface of a support; positioning of a portion of the element against the portion of the material; annealing of the material portion increasing, at the end of the treatment, the adhesion force of the material against the portion of the element, the materials of the portion of the element and of the portion of the surface of the support being selected such that the adhesion of the material against the portion of the element is, at the end of the annealing, higher than that of the material against the portion of the surface of the support; and separation of the element and the support at the interface between the material and the portion of the surface of the support, the material remaining secured to the portion of the element.

Cascode semiconductor

This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

Cascode semiconductor

This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

Heterogeneous antenna in fan-out package

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Heterogeneous antenna in fan-out package

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Method for manufacturing semiconductor package
11527503 · 2022-12-13 · ·

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

Method for manufacturing semiconductor package
11527503 · 2022-12-13 · ·

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

VERTICAL SEMICONDUCTOR DEVICE WITH SIDE GROOVES

A semiconductor device is vertically mounted on a medium such as a printed circuit board (PCB). The semiconductor device comprises a block of semiconductor dies, mounted in a vertical stack without offset. Once formed and encapsulated, side grooves may be formed in the device exposing electrical conductors of each die within the device. The electrical conductors exposed in the grooves mount to electrical contacts on the medium to electrically couple the semiconductor device to the medium.