A method for making integrated circuit (IC) packages includes providing a leadframe strip having a plurality of leadframe units and providing the leadframe strip to an operating station. The operating station is operable to perform one or more tests on the plurality of leadframe units in the making of IC packages. The method includes obtaining a database that has the locations of leadframe units in the leadframe strip stored in the database. The method also includes performing the one or more tests on the plurality of leadframe units and updating the database in response to the results of the testing.

A method for producing a bondable coating on a metallic carrier strip made of a brass alloy with at least 15 wt. % zinc or an excretion-hardening copper-based alloy containing at least 0.03 wt. % titanium, chromium, zirconium and/or cobalt is provided. According to the method, in a single working step, a bondable metallic functional layer made of aluminum or an aluminum-based alloy and a metallic intermediate layer are placed onto the metallic carrier strip and bonded thereto using a roll cladding method. The intermediate layer is arranged fully between the functional layer and the metallic carrier strip, so that no contact between the functional layer and the metallic carrier strip is created. A coated carrier strip produced using such a method. The intermediate layer is arranged and affixed on the carrier strip and the functional layer is arranged and affixed on the intermediate layer.

Disclosed is a COB die bonding and wire bonding system and method. The system comprises a controller, a forward die bonder, a reverse die bonder and a conveyor belt, the controller being connected with the forward die bonder and the reverse die bonder respectively, and the forward die bonder is associated with the reverse die bonder by the conveyor belt. The system and method can realize the combination of the forward and reverse bonding when using the forward die bonder and the reverse die bonder to fix the chips, thus the amount of gold wire used for connecting chips on a substrate is minimized. The COB die bonding and wire bonding system and method can be widely used in the field of electronics.

A method of manufacturing a semiconductor package includes; bonding a plurality of semiconductor chips to a plurality of mounting regions on a wiring board partitioned by crossing streets; supplying a liquid resin to a front surface side of the wiring board onto which the plurality of semiconductor chips have been bonded, to seal the plurality of semiconductor chips in a collective manner, thereby forming a sealed board; cutting the sealed board along the regions corresponding to the streets, to individualize the sealed chips in such a manner that the sealed chips each have an upper surface and a lower surface larger than the upper surface, with a side surface inclined from the upper surface toward the lower surface; and forming a conductive shield layer on the upper surfaces and the side surfaces of the plurality of sealed chips.

A ribbon bonding tool is provided. The ribbon bonding tool includes a body portion including a tip portion, the tip portion defining a working surface. The ribbon bonding tool includes a group of four protrusions extending from the working surface, wherein the working surface defines four quadrants in a horizontal plane by extending an imaginary line at a midpoint along each of a length and a width of the working surface. Each of the four protrusions is arranged in one of four quadrants.

A ribbon bonding tool is provided. The ribbon bonding tool includes a body portion including a tip portion, the tip portion defining a working surface. The ribbon bonding tool includes a group of four protrusions extending from the working surface, wherein the working surface defines four quadrants in a horizontal plane by extending an imaginary line at a midpoint along each of a length and a width of the working surface. Each of the four protrusions is arranged in one of four quadrants.

A method for making integrated circuit (IC) packages includes providing a leadframe strip having a plurality of leadframe units and providing the leadframe strip to an operating station. The operating station is operable to perform one or more tests on the plurality of leadframe units in the making of IC packages. The method includes obtaining a database that has the locations of leadframe units in the leadframe strip stored in the database. The method also includes performing the one or more tests on the plurality of leadframe units and updating the database in response to the results of the testing.

Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.

A method of manufacturing a semiconductor package includes: bonding a plurality of semiconductor chips to a plurality of mounting regions on a wiring board partitioned by crossing streets; supplying a liquid resin to a front surface side of the wiring board onto which the plurality of semiconductor chips have been bonded, to seal the plurality of semiconductor chips in a collective manner, thereby forming a sealed board; cutting the sealed board along the regions corresponding to the streets, to individualize the sealed chips in such a manner that the sealed chips each have an upper surface and a lower surface larger than the upper surface, with a side surface inclined from the upper surface toward the lower surface; and forming a conductive shield layer on the upper surfaces and the side surfaces of the plurality of sealed chips.

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.