A test wafer according to an embodiment of the present disclosure is a test wafer used for simulation of heat emission of devices on a wafer, and includes a silicon wafer and a silicon heater bonded to a surface of the silicon wafer.

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Provided are: a laminated semiconductor which enables curbing of manufacturing cost; a wafer laminate; a method for manufacturing the laminated semiconductor; an assistance device; and a program. This laminated semiconductor formed by laminating a plurality of chips is provided with: a logic chip; and a memory part that is stacked on the logic chip and has at least one memory chip communicable with the logic chip. The memory chip has: at least two memory bodies that have memory circuits and that are arranged side by side in a direction intersecting the stacking direction; and a connection part which is provided with a prescribed width between the memory bodies and which connects the memory bodies arranged side by side.

Provided are: a laminated semiconductor which enables curbing of manufacturing cost; a wafer laminate; a method for manufacturing the laminated semiconductor; an assistance device; and a program. This laminated semiconductor formed by laminating a plurality of chips is provided with: a logic chip; and a memory part that is stacked on the logic chip and has at least one memory chip communicable with the logic chip. The memory chip has: at least two memory bodies that have memory circuits and that are arranged side by side in a direction intersecting the stacking direction; and a connection part which is provided with a prescribed width between the memory bodies and which connects the memory bodies arranged side by side.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

A wafer laminating method includes a cooling step of cooling a first wafer, a laminating step of producing a laminated wafer by stacking and laminating a second wafer on a surface of the first wafer when condensation forms on the surface of the cooled first wafer, and a heat treatment step of subjecting the laminated wafer to heat treatment.

A wafer laminating method includes a cooling step of cooling a first wafer, a laminating step of producing a laminated wafer by stacking and laminating a second wafer on a surface of the first wafer when condensation forms on the surface of the cooled first wafer, and a heat treatment step of subjecting the laminated wafer to heat treatment.

A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.