Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.

A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.

A semiconductor device may include a first substrate structure including a plate layer, gate electrodes stacked on the plate layer, channel structures penetrating through the gate electrodes, and first bonding metal layers on the channel structures; and a second substrate structure connected to the first substrate structure, and including a substrate having active regions, device isolation layers in the substrate defining the active regions, circuit devices on one surface of the substrate, and second bonding metal layers connected to the first bonding metal layers, the device isolation layers including first device isolation layers and a second device isolation layer having different heights, and the active regions including first active regions spaced apart by the first device isolation layers and connected to each other by the substrate, and second active regions separated from the first active regions by the second device isolation layer.

Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

A 3D IC package includes a bottom die having a back interconnect side opposing a front device side, the back interconnect side having a plurality of bottom die interconnects extending thereto. A top die has a front device side opposing a back side, the front device side having a plurality of top die interconnects. An interposer includes a redistribution layer (RDL) between the bottom die and the top die, the RDL including a plurality of wiring layers extending from back side RDL interconnects thereof to front side RDL interconnects thereof. An under bump metallization (UBM) couples the back side RDL interconnects to the plurality of top die interconnects at a first location, and the front side RDL interconnects are coupled to the plurality of bottom die interconnects at a second location. The first location and second location may not overlap.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.