H01L2224/80908

BONDING APPARATUS AND METHOD OF CONTROLLING THE SAME

Provided are a bonding apparatus and a method of controlling the bonding apparatus. The bonding apparatus includes a bonding head, a wafer chuck configured to receive a wafer thereon, and at least one bonding stage cover disposed above the wafer chuck.

Semiconductor storage device including first pads on a first chip that are bonded to second pads on a second chip
11482514 · 2022-10-25 · ·

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

PROCESSES AND APPLICATIONS FOR CATALYST INFLUENCED CHEMICAL ETCHING

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

APPARATUS FOR BONDING CHIP BAND AND METHOD FOR BONDING CHIP USING THE SAME
20230163094 · 2023-05-25 ·

A chip bonding apparatus, includes: a body; a substrate conveyor installed on the body to transfer a substrate; a bonding head conveyor disposed on an upper surface of the body; an alignment unit installed on the body and adjusting a position of the substrate and a position of a chip; and a bonding head installed in the bonding head conveyor and moved and attaching a chip therebelow, wherein the bonding head is provided with a chip bonding unit for attaching the chip in a lower end portion thereof, wherein the chip bonding unit, includes: a chip bonding unit body having an installation groove formed therein; a pushing module having one end portion inserted in the installation groove; and an attachment module having a deformable member deformed by the pushing module; wherein the deformable member is provided with a deformable portion which is deformed by being pressed by the pushing module, and having a bottom surface in contact and exerting a force on the chip to bond the chip to the substrate.

DEVICE AND METHOD FOR THE ALIGNMENT OF SUBSTRATES

The invention relates to a device and a method for the alignment of substrates.

SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
20230197672 · 2023-06-22 · ·

In one embodiment, a semiconductor manufacturing apparatus includes a magnification difference acquirer configured to acquire a value of difference in magnification between a first substrate and a second substrate. The apparatus further includes a deformation amount determiner configured to determine a value of deformation amount of a chuck that holds the first or second substrate, based on the value of the difference in magnification. The apparatus further includes a gap determiner configured to determine a value of a gap between the first substrate and the second substrate, based on the value of the deformation amount. The apparatus further includes a bonding controller configured to control the deformation amount to the determined value and control the gap to the determined value, before the first substrate and the second substrate are bonded together.

Integrated Circuit Package and Method
20220384382 · 2022-12-01 ·

In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

BOND ENHANCEMENT FOR DIRECT-BONDING PROCESSES

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

Method and apparatus for determining expansion compensation in photoetching process, and method for manufacturing device

A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer.

Bonding method, storage medium, bonding apparatus and bonding system

There is provided a method of bonding substrates to each other, which includes: holding a first substrate on a lower surface of a first holding part; adjusting a temperature of a second substrate by a temperature adjusting part to become higher than a temperature of the first substrate; holding the second substrate on an upper surface of a second holding part; inspecting a state of the second substrate by imaging a plurality of reference points of the second substrate with a first imaging part, measuring positions of the reference points, and comparing a measurement result with a predetermined permissible range; and pressing a central portion of the first substrate with a pressing member, bringing the central portion of the first substrate into contact with a central portion of the second substrate, and sequentially bonding the first substrate and the second substrate.