A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

A light emitting device includes a carrier, a plurality of light emitting diode chips and a plurality of buffer pads. Each light emitting diode chip includes a first type semiconductor layer, an active layer, a second type semiconductor layer, a via hole and a plurality of bonding pads. The via hole sequentially penetrates through the first type semiconductor layer, the active layer and a portion of the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the via hole define a epitaxial structure. The buffer pads are disposed between the carrier and the second type semiconductor layer, wherein the buffer pads is with Young's modulus of 2˜10 GPa, the second bonding pad is disposed within the via hole to contact the second type semiconductor layer, and the epitaxial structure is electrically bonded to the receiving substrate through the bonding pads.

A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.

To reduce the manufacturing cost of a display device using a micro LED as a display element. To manufacture a display device using a micro LED as a display element in a high yield. Employed is a method for manufacturing a display device, including: forming a plurality of transistors in a matrix over a substrate (800), forming conductors (21, 23) electrically connected to the transistors over the substrate (800), and forming a plurality of light-emitting elements (51) in a matrix over a film (927). Each of the light-emitting elements (51) includes electrodes (85, 87) on one surface and the other surface is in contact with the film (927). The conductors (21, 23) and the electrodes (85, 87) are opposed to each other. An extrusion mechanism (929) is pushed out from the film (927) side to the substrate (800) side so that the conductors (21, 23) and the electrodes (85, 87) are in contact with each other, whereby the conductors (21, 23) and the electrodes (85, 87) are electrically connected to each other.

A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, and a third LED sub-unit disposed on the second LED sub-unit, in which the third LED sub-unit is configured to emit light having a shorter wavelength than that of light emitted from the first LED sub-unit, and to emit light having a longer wavelength than that of light emitted from the second LED sub-unit.

A method for manufacturing a display device can include growing a plurality of light emitting (LEDs) on a growing substrate; forming a member having a thermal flow characteristic on at least one side surface of each of the plurality of LEDs; separating each of the plurality of LEDs from the growing substrate; forming a plurality of assembly grooves in a wiring substrate for defining pixel regions; assembling the plurality of LEDs at locations respectively corresponding to the plurality of assembly grooves; and applying heat to the wiring substrate to perform a reflow process for adjusting a position of at least one of the plurality of LEDs.

A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

A flexible electronic structure includes a first film, made of a first polymer or glass, and a second film, made of a second polymer, in which at least one electronic component is arranged. The second film covers the first film. The flexible electronic structure also includes at least one electrically conductive track arranged between the first film and the second film, and each electrically connected to one of the electronic components, by a respective interconnection element. Optionally, the flexible electronic structure includes a third film, made of a third polymer or glass, covering the second film. The interconnection element is arranged near the neutral plane of the structure, and the structure includes at least one compensation layer, so as to position the neutral plane at a desired location.