H01L2224/8112

Bonding package components through plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Acrylic resin composition for sealing, cured product of same, method for producing same, semiconductor device using said resin composition, and method for manufacturing said semiconductor device

A sealing acrylic resin composition contains a thermosetting acrylic resin in liquid phase, an organic peroxide, and an inorganic filler in a content proportion ranging from 50% by mass to 95% by mass, inclusive. A silane coupling agent is bonded to the inorganic filler, a total organic carbon content of the inorganic filler in proportion being ranging from 0.1% by mass to 1.0% by mass, inclusive, in a state before the inorganic filler is mixed with at least one of the thermosetting acrylic resin and the organic peroxide. The silane coupling agent has an acrylic group.

Acrylic resin composition for sealing, cured product of same, method for producing same, semiconductor device using said resin composition, and method for manufacturing said semiconductor device

A sealing acrylic resin composition contains a thermosetting acrylic resin in liquid phase, an organic peroxide, and an inorganic filler in a content proportion ranging from 50% by mass to 95% by mass, inclusive. A silane coupling agent is bonded to the inorganic filler, a total organic carbon content of the inorganic filler in proportion being ranging from 0.1% by mass to 1.0% by mass, inclusive, in a state before the inorganic filler is mixed with at least one of the thermosetting acrylic resin and the organic peroxide. The silane coupling agent has an acrylic group.

PROCESS FOR PACKAGING COMPONENT

A process for packaging at least one component includes the steps of: a) providing a substrate and a packaging material layer, b) forming the packaging material layer into an adhesively semi-cured packaging material layer, c) adhering the adhesively semi-cured packaging material layer to an array, d) providing a packaging unit including at least one eutectic metal bump pair, e) permitting the eutectic metal bump pair to be in contact with at least one electrode pair on the array, f) subjecting the electrode pair to eutectic bonding to the eutectic metal bump pair, g) encapsulating the component by pressing, h) completely curing the adhesively semi-cured packaging material layer, and i) removing the substrate.

Interconnect using embedded carbon nanofibers
10658349 · 2020-05-19 · ·

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

SYSTEM AND METHOD FOR SUPERCONDUCTING MULTI-CHIP MODULE

A method for bonding two superconducting integrated circuits (chips), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

METHOD FOR PRODUCING A MICROELECTRONIC CHIP TO BE HYBRIDISED TO A SECOND CHIP

The invention relates to a method for producing a first microelectronic chip including a layer of interest having a connection face, intended to be hybridized with a second microelectronic chip. The method including depositing a layer of adhesive on a face of the layer of interest opposite to the first connection face and fastening a handle layer to the layer of adhesive. The method also includes, prior to the steps of depositing the adhesive and fastening the handle layer, defining, on the one hand, a maximum thickness e.sub.cc.sup.max and a minimum value E.sub.cc.sup.min and a maximum value E.sub.cc.sup.max of the Young's modulus for the layer of adhesive, and, on the other hand, the minimum thickness e.sub.cp.sup.min for the handle layer.

METHOD FOR PRODUCING A MICROELECTRONIC CHIP TO BE HYBRIDISED TO A SECOND CHIP

The invention relates to a method for producing a first microelectronic chip including a layer of interest having a connection face, intended to be hybridized with a second microelectronic chip. The method including depositing a layer of adhesive on a face of the layer of interest opposite to the first connection face and fastening a handle layer to the layer of adhesive. The method also includes, prior to the steps of depositing the adhesive and fastening the handle layer, defining, on the one hand, a maximum thickness e.sub.cc.sup.max and a minimum value E.sub.cc.sup.min and a maximum value E.sub.cc.sup.max of the Young's modulus for the layer of adhesive, and, on the other hand, the minimum thickness e.sub.cp.sup.min for the handle layer.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Semiconductor Device and Method of Manufacture
20200006241 · 2020-01-02 ·

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.