A laser compression bonding device and method for a semiconductor chip are proposed. The device includes a conveyor unit that transports a semiconductor chip and a substrate, and a bonding head that includes a bonding tool for applying a pressure to the chip and substrate, a laser beam generator for emitting a laser beam, a thermal imaging camera for measuring temperatures of the surfaces of semiconductor chip and substrate, and a compression unit for controlling a pressure applied by the bonding tool and a position thereof, wherein the compression unit includes a mount on which the bonding tool is detachably mounted, and a servo motor and a load cell that apply a pressure to the mount or control a position thereof. The servo motor is controlled with two values for pressure application and positioning.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.

A film structure, a chip carrier assembly, and a chip carrier device are provided. The film structure includes a film and a plurality of micro-heaters. In which, the film is applied on a substrate, and the plurality of micro-heaters is disposed on top of the film or in the film. The chip carrier assembly includes a circuit substrate and the film structure. In which, the circuit substrate carries a plurality of chips. The chip carrier device includes the chip carrier assembly and a suction unit. In which, the suction unit is arranged above the chip carrier assembly to attach on and transfer the plurality of chips to the circuit substrate. The chips are disposed on the circuit substrate through solder balls, and the micro-heaters heat the solder balls that are in contact with the chips.

A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.

An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.

A resin shaping device configured to cure a resin placed in a mold in a state in which the mold is pressed against a substrate, the resin shaping device comprising: a substrate holding unit configured to hold the substrate in an orientation such that a forming face for forming a resin part on the substrate faces vertically downward; a head configured to hold the mold from vertically below; a head drive unit configured to cause the head to face a position for formation of a resin part on the substrate, and then cause vertically upward movement of the head so that the head approaches the substrate holding unit and presses the mold from vertically below the substrate; and a resin curing unit configured to cure the resin placed in the mold in a state in which the mold is pressed against the substrate.

A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a bond head assembly for bonding a semiconductor element to a substrate at a bonding area of the bonding system; a reducing gas delivery system for providing a reducing gas to the bonding area during bonding of the semiconductor element to the substrate; and a gas composition analyzer configured for continuously monitoring a composition of the reducing gas during operation of the bonding system.

Provided is a flip-chip bonding apparatus using VCSEL device, and more particularly, to a flip-chip bonding apparatus using VCSEL device for bonding a flip-chip type semiconductor chip to a substrate using infrared laser light generated from the VCSEL device. The flip-chip bonding apparatus using VCSEL device may quickly control laser light to bond a semiconductor chip to a substrate, with high productivity and high quality.

A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first and second package components stacked upon and electrically connected to each other. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps, and dimensions of the first and second conductive bumps are less than those of the third and fourth conductive bumps. The semiconductor package includes a first joint structure partially wrapping the first conductive bump and the third conductive bump, and a second joint structure partially wrapping the second conductive bump and the fourth conductive bump. A curvature of the first joint structure is different from a curvature of the second joint structure.