A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

To reduce the height of a semiconductor apparatus formed by stacking semiconductor chips. The semiconductor apparatus includes: a first package; a second package; and a connection part. The first package includes a substrate on which a first semiconductor chip and a first wiring connected to the first semiconductor chip are disposed. The second package includes a second semiconductor chip that exchanges a signal with the first semiconductor chip and has a surface on which a pad for transmitting the signal is formed, a sealing part that covers the second semiconductor chip while exposing at least a part of the surface of the second semiconductor chip, an insulation layer that is formed on the surface of the second semiconductor chip and a surface of the sealing part adjacent to the surface of the second semiconductor chip, and a second wiring that is connected to the pad via an opening disposed in the insulation layer and formed adjacent to the insulation layer, and transmits the signal. The connection part is disposed between the substrate and the sealing part and connects the first wiring and the second wiring to each other.

A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer.

A high-frequency module includes a semiconductor element, a first insulating layer, an acoustic wave element, a second insulating layer, a first intermediate layer, and a second intermediate layer. The first intermediate layer is interposed between the acoustic wave element and the semiconductor element, and has a thermal conductivity lower than the first and second insulating layers. The second intermediate layer is interposed between the first insulating layer and the second insulating layer, and has a thermal conductivity lower than the first and second insulating layers. A step is provided between a first principal surface of the first insulating layer and one principal surface of the semiconductor element. The distance between first and second principal surfaces of the first insulating layer is greater than the distance between the second principal surface of the first insulating layer and the one principal surface of the semiconductor element.

A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.

An electrical conductor structure comprises a substrate and an electrical conductor disposed on or in the substrate. The electrical conductor comprises a first layer and a second layer disposed on a side of the first layer opposite the substrate. The first layer comprises a first electrical conductor that forms a non-conductive layer on a surface of the first electrical conductor when exposed to air and the second layer comprising a second electrical conductor that does not form a non-conductive layer on a surface of the second electrical conductor when exposed to air. A component comprises a connection post that is electrically connected to the second layer and the electrical conductor. The first and second layers can be inorganic. The first layer can comprise a metal such as aluminum and the second layer can comprise an electrically conductive metal oxide such as indium tin oxide.

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A high-frequency module includes a semiconductor element, a first insulating layer, an acoustic wave element, a second insulating layer, a first intermediate layer, and a second intermediate layer. The first intermediate layer is interposed between the acoustic wave element and the semiconductor element, and has a thermal conductivity lower than the first and second insulating layers. The second intermediate layer is interposed between the first insulating layer and the second insulating layer, and has a thermal conductivity lower than the first and second insulating layers. A step is provided between a first principal surface of the first insulating layer and one principal surface of the semiconductor element. The distance between first and second principal surfaces of the first insulating layer is greater than the distance between the second principal surface of the first insulating layer and the one principal surface of the semiconductor element.